33M Full-Frame CCD Image Sensor

33M Full-Frame CCD Image Sensor

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Contents:
IMAGE SENSORS

DATA SHEET

FTF5066C 33M Full-Frame CCD Image Sensor
Product specification 2006, October 30

DALSA Professional Imaging

DALSA Professional Imaging

Product Specification

33M Full-Frame CCD Image Sensor

FTF5066C

� � � � � � � � � � � � � � � � � �

Image format (36 x 48 mm ) 33M active pixels (4992H x 6668V) RGB Bayer pattern Progressive scan Excellent antiblooming Variable electronic shuttering Square pixel structure H and V binning Vertical subsampling 70% fill factor High linear dynamic range (>70dB) High sensitivity Low dark current and fixed pattern noise Low readout noise Data rate up to 27 MHz per output Mirrored and split readout Perfectly matched to visual spectrum RoHS compliant

2

Description
The FTF5066C is a full frame CCD colour image sensor designed for professional digital photography applications, with very low dark current and a linear dynamic range of over 12 true bits at room temperature. The four low-noise output amplifiers, one at each corner of the chip, make the FTF5066C suitable for a wide range of high-end visual light applications. With one output amplifier, a progressively scanned image can be read out at 0.7 frames per second. By using two outputs, the frame rate increases accordingly. The device structure is shown in figure 1.

Z

Device structure
Optical size: Chip size: Pixel size: Active pixels: Total no. of pixels: Optical black pixels: Overscan pixels: Dummy lines: Optical black lines: Dummy register cells: 35.942 mm (H) x 48.010 mm (V) 37.670 mm (H) x 49.496 mm (V) 7.2 x�m x 7.2 �m 4992 (H) x 6668 (V) 5040 (H) x 6726 (V) Left: 20 Right: 20 Left: 4 Right: 4 Bottom: 23 Top: 23 Bottom: 6 Top: 6 Left: 9 Right: 9

G B G B R G R G G B G B

23 Dummy Lines 6 black lines

G B G B R G R G G B G B

Y

6668 active lines

6726 lines

Image Area

20 4
G B G B R G R G

4992 active pixels 6 black lines 23 Dummy Lines 5040 cells Output register 5058 cells

4 20
G B G B R G R G

W 9 Output amplifier

X
9

Figure 1 - Device structure

October 30, 2006

2

DALSA Professional Imaging

Product Specification

33M Full-Frame CCD Image Sensor

FTF5066C

Architecture of the FTF5066C
The optical centers of all pixels in the image section form a square grid. The charge is generated and integrated in this section. Output registers are located below and above the image section for readout. After the integration time, the image charge is shifted one line at a time to either the upper or lower register or to both simultaneously, depending on the readout mode. A separate transfer gate (TG) between the image section and output register will enable sub-sampling features. The left and right half of each register can be controlled independently. This enables either single or multiple read-out. During vertical transport, the C3 gates separate the pixels in the register. The central C3 gates of the lower and upper registers are part of the left half of the sensor (W and Z quadrants respectively). Each register can be used for vertical binning. Each register contains a summing gate at both ends that can be used for horizontal binning (see figure 2).

IMAGE SECTION Image diagonal (active video only) Aspect ratio Active image width x height Pixel width x height Fill factor Image clock pins Capacity of each clock phase Number of active lines Number of black lines Number of dummy lines Total number of lines Number of active pixels per line Number of over scan (timing) pixels per line Number of black reference pixels per line Total number of pixels per line 59.9 mm 3:4 35.942 x 48.010 mm2 7.2 x 7.2 �m2 70% 16 pins (A1...A4) 40nF per pin 6668 12 (=2x6) 46 (=2x23) 6726 4992 8 (2x4) 40 (2x20) 5040

OUTPUT REGISTERS Output buffers on each corner Number of registers Number of dummy cells per register Number of register cells per register Output register horizontal transport clock pins Capacity of each C-clock phase Overlap capacity between neighboring C-clocks Output register Summing Gates Capacity of each SG Reset Gate clock phases Capacity of each RG Three-stage source follower 2 18 (2x9) 5058 (5040 + 18) 6 pins per register (C1...C3) 200 pF per pin 40 pF 4 pins (SG) 15pF 4 pins (RG) 15pF

October 30, 2006

3

DALSA Professional Imaging

Product Specification

33M Full-Frame CCD Image Sensor

FTF5066C

9 dummy pixels
OG SG C2 C1 C3

20 black & 4 overscan columns

5000 image pixels

20 black & 4 overscan columns

9 dummy pixels
RD RG C2 C1 SG OG

C2 C1 C3 C2 C1 C3 C2 C1 C3

C2 C1 C3 C2 C1 C3

C2 C1 C3 C2 C1 C3

C2 C1 C3 C2 C1 C3 C2 C1 C3

OUT_Z

A2 A3 A4

23 dummy lines 6 black lines

A2 A3 A4

OUT_Y

A1 A2 A3 A4 A1 A2 A3 A4

A1 A2 A3 A4 A1 A2 A3 A4

One Pixel

SG: summing gate OG: output gate RG: reset gate RD: reset drain TG: transfer gate
A1 A2 A3 A4 A1 A2 A3 A4

6668 active image lines

IMAGE
FTF CCD

A1 A2 A3 A4 A1 A2 A3 A4

6 black lines

A1 A2 A3 A4

23 dummy lines
C2 C1 C3 C2 C1 C3 C3 C2 C1 C3 C2 C1 C3

A1 A2 A3 A4

OUT_W
OG SG C2 C1 C3 RG RD

OUT_X
C2 C1 SG OG

C2 C1 C3 C2 C1 C3 C2 C1 C3

C2 C1 C3 C2 C1 C3 C2 C1 C3

column 1

column 24 + 1

column 24 + 4998

column 24 +4998 +24

A1, A2, A3, A4: clocks of image section

C1, C2, C3: clocks of horizontal registers

Figure 2 - Detailed internal structure

October 30, 2006

4

DALSA Professional Imaging

Product Specification

33M Full-Frame CCD Image Sensor
Specifications
ABSOLUTE MAXIMUM RATINGS1 GENERAL: Storage temperature Ambient temperature during operation Voltage between any two gates DC current through any clock phase (absolute value) OUT current (no short circuit protection) VOLTAGES IN RELATION TO VPS: VNS, SFD, RD VCS, SFS All other pins VOLTAGES IN RELATION TO VNS: SFD, RD VCS, SFS, VPS All other pins VOLTAGES IN RELATION TO SFD: RD DC CONDITIONS VNS4 VPS SFD SFS VCS OG RD
2,3

FTF5066C

MIN

MAX

UNIT

-40 -20 -20 -0.2 0 -0.5 -8 -20 -15 -30 -30 -5 MIN [V] 20 5.5 19.5 0 0 4.75 19.5
2

+80 +60 +20 +0.2 +10 +30 +5 +25 +0.5 +0.5 +0.5 0 TYPICAL [V] 26 6 20 0 0 5.0 20 TYPICAL MAX [V] 28 6.5 20.5 0 0 5.25 20.5 MAX

�C �C V �A mA V V V V V V V MAX [mA] 15 15 4.5 1 - - - UNIT

N substrate P substrate Source Follower Drain Source Follower Source Current Source Output Gate Reset Drain

AC CLOCK LEVEL CONDITIONS

MIN

IMAGE CLOCKS/ TRANSFER GATES5: A-clock amplitude during integration A-clock amplitude during vertical transport (duty cycle=5/8) 6 A-clock low level Charge Reset (CR) level on A-clock7 OUTPUT REGISTER CLOCKS: C-clock amplitude (duty cycle during hor. transport=3/6) C-clock low level Summing Gate (SG) amplitude Summing Gate (SG) low level OTHER CLOCKS: Reset Gate (RG) amplitude Reset Gate (RG) low level Charge Reset (CR) pulse on Nsub7
1

8 11 -5 4.75 4.75 5 0

8 11 0 0 5 3 5 4.5 5 17 5

8.5 11.5 5.25 10 10 5

V V V V V V V V V V V

During Charge Reset it is allowed to exceed maximum rating levels (see note 7) 2 All voltages in relation to SFS; typical values are according to test conditions 3 Power-up sequence: VNS, SFD, RD, VPS, all others. The difference between SFD and RD should not exceed 5V during power up or down. 4 To set the VNS voltage for optimal Vertical Antiblooming (VAB), it should be adjustable between minimum and maximum values 5 Transfer gate should be clocked as A1 during normal transport or held low during a line shift to sub-sample image 6 Three-level clock is preferred for maximum charge; the swing during vertical transport should be 3V higher than the voltage during integration A two level clock (typically 10V) can be used if a lower maximum charge handling capacity is allowed 7 Charge Reset can be achieved in two ways of which the first method is preferred: A. The typical A-clock low level is applied to all image clocks for proper CR, an additional Charge Reset pulse on VNS is required B. The minimum CR level is applied to all image clocks simultaneously

October 30, 2006

5

DALSA Professional Imaging

Product Specification

33M Full-Frame CCD Image Sensor
Timing diagrams (for default operation)
AC CHARACTERISTICS Horizontal frequency (1/Tp) Vertical frequency Charge Reset (CR) time Rise and fall times: image clocks (A) register clocks (C)2 summing gate (SG) reset gate (RG)
1 2 1

FTF5066C

MIN 10 10 3 3 -

TYPICAL 25 50 Line time 20 5 5 3

MAX 27 300 1/8 Tp 1/8 Tp 1/8 Tp

UNIT MHz kHz �s ns ns ns ns

TP = 1 clock period Duty cycle = 3/6

integration

6703 image lines

idle
CR

integration

23 dummy

6 black
27 28 29 30 31

6668 active lines

6 black
6695 6696 6697 6698 6699 6700 6701 6702 6703 1 1 1

22 23 24 25 26

1 1 1 1 1 1 2 3

SSC NS puls/CR Trig_in VA high TG/A1 A2 A3 A4

H L H L H L H L H L H L H L H L CR

REMARKS * CR is applied during the first line after the transition from L to H of Trig_in * CCD is integrating during high period of Trig_in * After readout sequence the timing will go into idle mode.

Figure 3: Frame Timing Diagram

October 30, 2006

1 1 1 1 1

6

DALSA Professional Imaging

Product Specification

33M Full-Frame CCD Image Sensor
Line Timing, Single Output Mode

FTF5066C

5713 5717 0

Pixelnumbers represent the beginning of the concerning pixel

Sensor Output

Active Pixels
4992

688 697 717 721 B
9 dummy 20 black

B
20 4 black timing

Active Pixels
4992 4 overscan

SSC VA high TG/A1 A2 A3 A4

H L H L H L H L H L H L 7.5us 125 188

7.5us 250

7.5us 375

7.5us

15us

REMARKS * Thorizontal = 5737 * 1/25E6 = 229us * Vertical transport frequency = 50kHz

Line Timing, Dual Output Mode
Pixelnumbers represent the beginning of the concerning pixel

563

10us

438

5us

313

12.5us

501

27.5us

Sensor Output

Active Pixels
2496

0

688 697 717 721 B
20 black 9 dummy

688

27.5us

688

Falling edge of pixel 5737

Rising edge of pixel 0

Active Pixels
2496 4 overscan

SSC VA high TG/A1 A2 A3 A4

H L H L H L H L H L H L 7.5us 125 188

7.5us 250

7.5us 375

7.5us

15us

REMARKS * Thorizontal = 3217 * 1/25E6 = 129us * Vertical transport frequency = 50kHz

Figure 4: Vertical Readout, Single and Dual Output Modes

October 30, 2006

563

10us

438

5us

313

12.5us

501

27.5us

688

27.5us

688

Falling edge of pixel 3217

Rising edge of pixel 0

7

DALSA Professional Imaging

Product Specification

33M Full-Frame CCD Image Sensor

FTF5066C

Pixel Timing
SSC C3 C1 C2 SG RG SINGLE OUTPUT
9 dummy 20 black 4 overscan
R G G B R G G B R G G B R G G B

SSC clocked with rising edge of C2

4992 active
R G G B R G G B

4 overscan
R G G B R G G B

20 black

DUAL OUTPUT

9 dummy

20 black

4 overscan
R G G B R G G B R G G B R G G B

2496 active
R G G B R G G B R G G B R G G B

SENSOR PIN SINGLE OUTPUT Left SINGLE OUTPUT Right DUAL OUTPUT

C1L C2L C3L C1R C2R C3R C1 C2 C3 C1 C2 C3 C2 C1 C3 C2 C1 C3 C1 C2 C3 C2 C1 C3

40ns 20ns

C3 C1 C2 SG RG Sensor output

H L 13.33ns H L 26.67ns H L H L 6.67ns H L

PHIC'S @ 25MHz

RG black signal

Figure 5: Horizontal Readout, Single and Dual Output Modes

October 30, 2006

8

DALSA Professional Imaging

Product Specification

33M Full-Frame CCD Image Sensor

FTF5066C

Performance
The test conditions for the performance characteristics are as follows: � All values are measured using typical operating conditions. � VNS is adjusted as low as possible while maintaining proper Vertical Antiblooming � Sensor temperature = 60�C (333K) � Horizontal transport frequency = 25MHz � Vertical transport frequency = 50kHz � Integration time = 100ms � Linear Operation, Linear/Saturation and Dark Condition parameters are measured at W and X output.

LINEAR OPERATION (W/X Output) Charge Transfer Efficiency Image lag Resolution (MTF) @ 70 lp/mm Quantum Efficiency in Red Quantum Efficiency in Green Quantum Efficiency in Blue Block-to-block difference Stitching effect Low Pass Shading2 Random Non-Uniformity (RNU)3
1 2 1

MIN 65 Tbd Tbd Tbd

TYPICAL 0.999999 0 22 15 15 1.0 1.0 2 1

MAX 0 -

UNIT % % % % %

3.0 3.0 5 2

% % % %

Charge Transfer Efficiency values are tested by evaluation and expressed as the value per gate transfer Low Pass Shading is defined as the ratio of the one- value of an 8x8 pixel blurred image (low-pass) to the mean signal value 3 RNU is defined as the ratio of the one- value of the high-pass image to the mean signal of nominal light

October 30, 2006

9

DALSA Professional Imaging

Product Specification

33M Full-Frame CCD Image Sensor

FTF5066C

2.0

2 outputs

1.5

1 output

Images/sec.

1.0

0.5

0.0 0 10 20 30 40 50 60 70 80 90 100 Integration Tim e (m s)

Figure 6: Maximum number of images/second versus integration time

100% 90% 80% 70%
Response (%)

Horizontal Vertical

60% 50% 40% 30% 20% 10% 0% 0 5 1 0 1 5
Angle of illumination (degrees) Figure 7 - Angular response versus angle of illumination

2 0

2 5

3 0

October 30, 2006

10

DALSA Professional Imaging

Product Specification

33M Full-Frame CCD Image Sensor

FTF5066C

25.00 R

20.00

Quantum Efficiency [%]

B 15.00

G

10.00

5.00

0.00 400.00

450.00

500.00

550.00

600.00 Wavelength [nm]

650.00

700.00

750.00

800.00

Figure 8 - Quantum efficiency versus wavelength

October 30, 2006

11

DALSA Professional Imaging

Product Specification

33M Full-Frame CCD Image Sensor

FTF5066C

LINEAR/SATURATION (W/X Output) Full-well capacity saturation level (Qmax)1 Full-well capacity linear operation (Qlin)2 Overexposure3 handling
1 2 3

MIN 2000 1800 -

TYPICAL 2200 1900 200

MAX -

UNIT mV mV x Qmax level

Qmax is determined from the low-pass filtered image The linear full-well capacity Qlin is calculated from linearity test (see dynamic range). The test guarantees 97% linearity. Overexposure over entire area while maintaining good Vertical Anti-Blooming (VAB) is tested by measuring the dark line along the image section.

2750

2200

Output Signal(mV)

1650

1100

550

0 0

1

2

3

4

5

Exposure (arbitrary units)

Figure 9 Charge handling Figure 9--Charge handling

October 30, 2006

12

DALSA Professional Imaging

Product Specification

33M Full-Frame CCD Image Sensor

FTF5066C

DARK CONDITION Dark current level @ 20�C Dark current level @ 60�C Fixed Pattern Noise (FPN) @ 60�C
1 1

MIN -

TYPICAL 3 0.1 20

MAX 7 0.2 40

UNIT pA/cm2 nA/cm2 mV/s

FPN is one- value of the high-pass image and normalized at 1 sec integration time

1000

Dark Current (pA/cm2)

100

10

1 0 10 20 30 Temp. (oC) 40 50 60

Figure Dark current versus temperature Figure 10-10 - Dark current versus temperature

OUTPUT BUFFERS Conversion factor Mutual conversion factor matching (ACF)1 Supply current Bandwidth (Rload=3.3 K) Output impedance buffer (Rload=3.3 K, Cload=2pF) Amplifier noise over full bandwidth after CDS
1

MIN 36 100 -

TYPICAL 40 0 4.5 130 400 0.7

MAX 44 5 -

UNIT �V/el. �V/el. mA MHz mV

Matching of the four outputs is specified as ACF with respect to reference measured at the operating point (Qlin/2)

October 30, 2006

13

DALSA Professional Imaging

Product Specification

33M Full-Frame CCD Image Sensor
Application information
Current handling One of the purposes of VPS is to drain the holes that are generated during exposure of the sensor to light. Free electrons are either transported to the VRD connection and, if excessive (from overexposure), free electrons are drained to VNS. No current should flow into any VPS connection of the sensor. During high overexposure, a total current of 5 to 10mA through all VPS connections together may be expected. The PNP emitter follower in the circuit diagram (figure 12) serves these current requirements. VNS drains superfluous electrons as a result of overexposure. In other words, it only sinks current. During high overexposure, a total current of 5 to 10mA through all VNS connections together may be expected. The clamp circuit, consisting of the diode and electrolytic capacitor, enable the addition of a Charge Reset (CR) pulse on top of an otherwise stable VNS voltage. To protect the CCD, the current resulting from this pulse should be limited. This can be accomplished by designing a pulse generator with a rather high output impedance. Decoupling of DC voltages All DC voltages (not VNS, which has additional CR pulses as described above) should be uncoupled with a 22nF uncoupling capacitor. This capacitor must be mounted as close as possible to the sensor pin. Further noise reduction (by bandwidth limiting) is achieved by the resistors in the connections between the sensor and its voltage supplies. The electrons that build up the charge packets that will reach the floating diffusions only add up to a small current, which will float through VRD. Therefore, a large series resistor in the VRD connection may be used. Outputs To limit the on-chip power dissipation, the output buffers are designed with open source outputs. Outputs to be used should therefore be loaded with a current source or more simply with a resistance to GND. In order to prevent the output (which typically has an output impedance of about 400 ) from bandwidth limitation as a result of capacitive loading, load the output with an emitter follower built from a

FTF5066C

high-frequency transistor. Mount the base of this transistor as close as possible to the sensor and keep the connection between the emitter and the next stage short. The CCD output buffer can easily be destroyed by ESD. By using this emitter follower, this danger is suppressed; do NOT reintroduce this danger by measuring directly on the output pin of the sensor with an oscilloscope probe. Instead, measure on the output of the emitter follower. Slew rate limitation is avoided by avoiding a too-small quiescent current in the emitter follower; about 10mA should do the job. The collector of the emitter follower should be uncoupled properly to suppress the Miller effect from the base-collector capacitance. A CCD output load resistor of 3K3 typically results in a bandwidth of 130 MHz for X, W, Y and Z output. Device protection The output buffers of the FTF5066C are likely to be damaged if VPS rises above SFD or RD at any time. This danger is most realistic during power-on or power-off of the camera. The RD voltage should always be lower than the SFD voltage. Never exceed the maximum output current. This may damage the device permanently. The maximum output current should be limited to 10mA. Be especially aware that the output buffers of these image sensors are very sensitive to ESD damage. Because of the fact that our CCD's are built on an n-type substrate, we are dealing with some parasitic npn transistors. To avoid activation of these transistors during switch-on and switch-off of the camera, we recommend the application diagram of figure 12. Unused sections To reduce power consumption, the following steps can be taken. Connect unused output register pins (C1...C3, SG, OG) and unused SFS pins to zero Volts.

Device Handling
An image sensor is an MOS device, which can be destroyed by electro-static discharge (ESD). Therefore, the device should be handled with care. Always store the device with short-circuiting clamps or on conductive foam. Always switch off all electric signals when inserting or removing the sensor into or from a camera (the ESD protection in the CCD image sensor process is less effective than the ESD protection of standard CMOS circuits). Being a high quality optical device, it is important that the cover glass remains undamaged. When handling the sensor, use finger cots. When cleaning the glass, we strongly recommend using ethanol. Use of other liquids is strongly discouraged: � � if the cleaning liquid evaporates too quickly, rubbing is likely to cause ESD damage. the cover glass and its coating can be damaged by other liquids.

Rub the window carefully and slowly. Dry rubbing of the window may cause electro-static charges or scratches, which can destroy the device.

October 30, 2006

14

From V-Driver

VSFD

NS

CR

A3

A2

A4

A1

TG

From PPG
VRD 22n NS_CR 47K 1u 22n 22n 35V NS NS_CR BAS28 VRD SG RG C1 C2 C3 B8 D10 E9 E10 F9 F10 G9 H9 J10 J9 K10 K9 L10 NS OG RD RG SG C1 C2 C3 C3 C2 C1 SG RG RD 22n OG SFD B10 OUTZ OUTY SFD VPS VNS VNS TG A4Y A3Y A2Y A1Y A1X A2X A3X A4X TG VNS VNS VPS SFD OUT OG SFS VCS RD RG SG C1 C2 C3 VNS VNS C3 C2 C1 SG RG RD VCS SFS OG P7 P8 N6 N5 P3 P4 N4 P5 M2 P1 P2 N2 N1 22n 22n N7 P6 P10 M9 P9 BAS28 NS 22n N9 SFD VPS VNS VNS TG A4Z A3Z A2Z A1Z A1W A2W A3W A4W TG VNS VNS VPS SFD OUT N10 B9 A9 C9 A10 A6 B7 A7 A8 VRD B6 B5 A3 VPS A4 B4 A5 C2 A1 A2 22n B2 22n B1 100E 3K3 BFR92 NS_CR BC860C BAT74 NS_CR 22n N8

SFS D9

VCS C10

VNS G10

VNS H10

VCS M10

VPS 22n BAS28 NS 22n

SFS L9

22K

BAT74

BAT74

CCD
image sensor

120K 20K

22n

56K

33M Full-Frame CCD Image Sensor

BAS28 NS 22n

NS_CR

BAS28 NS 22n

22n

2K2

B3

D2

C1

D1

E2

E1

F2

F1

G2

G1

H1

H2

J1

J2

K1

K2

L1

M1

L2

VOG 22n 22n

N3

22n

VOG

22n

Figure 11 � Application diagram for single output operation

31K5

NS

BAS28

BAS28

22n

October 30, 2006
SFD VPS NS_CR VPS VSFD CCD OUT H DRIVER VOG 1 VRD NS_CR VRD 22n 22n 74ACT04 H DRIVER 1 22n BAS28 100K 22n BAS28 100K 22n BAS28 100K 22n 74ACT04 H DRIVER 1 22n

DALSA Professional Imaging

BAT74

100K

9K

22n

7K5

100K

BAS28

0E

BAS28

22n

100K

12K

22n

BAS28

100K

BAS28

100K

Product Specification

FTF5066C

15

22n 74ACT04

DALSA Professional Imaging

Product Specification

33M Full-Frame CCD Image Sensor
Pin configuration
The FTF5066C is mounted in a Pin Grid Array (PGA) package with 80 pins in a 20x25 grid of 51.30 x 64.00mm2. The position of pin A1 (quadrant W) is marked with a gold SYMBOL VNS TG VNS VNS VPS SFD SFS VCS OG RD A1 A2 A3 A4 C1 C2 C3 SG RG OUT LINEAR/SATURATION N substrate Transfer Gate N substrate N substrate P substrate Source Follower Drain Source Follower Source Current Source Output Gate Reset Drain Image Clock (Phase 1) Image Clock (Phase 2) Image Clock (Phase 3) Image Clock (Phase 4) Register Clock (Phase 1) Register Clock (Phase 2) Register Clock (Phase 3) Summing Gate Reset Gate Output
A B C D E F G 10 9 8 7 6
VNS OUT VCS VPS SFD VNS A2 A3 TG OG A4 A1
A4

FTF5066C

dot on top of the package. The image clock phases of quadrant W are internally connected to X, and Y is connected to Z. PIN # W A1 A5 C2 G1 A2 B2 D2 C1 B3 D1 B5 A3 A4 B4 F2 F1 G2 E1 E2 B1 PIN # X P1 P5 M2 H1 P2 N2 L2 M1 N3 L1 N5 P3 P4 N4 J2 J1 H2 K1 K2 N1 PIN # Y P10 P6 M9 H10 P9 N9 L9 M10 N8 L10 N6 P8 P7 N7 J9 J10 H9 K10 K9 N10 PIN # Z A10 A6 C9 G10 A9 B9 D9 C10 B8 D10 B6 A8 A7 B7 F9 F10 G9 E10 E9 B10

H J K L M N P
VNS C3 C2 C1 SG RG RD VCS OUT VNS

RD SFS

SG RG

C2 C1

VNS C3

SFS VNS SFD VPS OG A4 A1 A2 A3 TG

OGSG

C1

C3

C1

C3

SG OG

A1

Z

TOP

A4
A1

Y

A4

A4

5 4 3 2 1

RD RG

W
OGSG C1

BOT
C3 C1 C3

X

A1

A1

RD RG SFD

TG A3 A2 VPS

A1 A4

SFD

A1 A4

TG A3 A2 VPS

SG OG
OUT

OUT

OG SFD

SFS

VCS

VCS

SFS

OG

VNS SFS RD

RG SG

C1 C2

C3 VNS

C3 VNS

C1 C2

RG SG

SFS VNS SFD RD

VNS OUT VCS

VCS OUT VNS

DOT ON TOP OF CCD INDICATES LOCATION OF PIN 1

Figure 12- Pin-configuration (top view) Figure 13 Pin configuration (top view)

October 30, 2006

16

DALSA Professional Imaging

Product Specification

33M Full-Frame CCD Image Sensor

FTF5066C

Package information
Top cover glass to top image sensor 1.68�0.20 Chip - bottom package 2.79�0.15 Image sensor Cover glass Cover glass 1.0�0.05

32�0.15

Image sensor

64�0.64

A

1.4/100

Top view Index mark pin 1

25.65�0.15 51.3�0.51

Cover glass

Stand-off pin

(2.54) 0.46�0.05

1.27�0.15

4.57�0.15

60.96�0.60

A is the center of the image area. Position of A: 25.65 � 0.15 to left edge of package 32.00 � 0.15 to upper edge of package 2.7 � 0.15 to bottom of package Angle of rotation: less than � 1� Sensor flatness: < 40 �m (P-V) Cover glass: Hoya CG1 Thickness of cover glass: 1 � 0.05 Refractive index: n d = 1.53 Double sided AR coating < 1% (430-660 nm) reflection Hermetically sealed package All drawing units are in mm

Bottom view

48.26

0.27

Figure 13- -Mechanical drawing of the PGA package Figure 14 Mechanical drawing of the PGA package

October 30, 2006

17

DALSA Professional Imaging

Product Specification

33M Full-Frame CCD Image Sensor
Order codes
The sensor can be ordered using the following code:

FTF5066C

Description
FTF5066C/HG FTF5066C/IG FTF5066C/EG FTF5066C/TG

FTF5066C sensor Quality Grade
High Grade Industrial Grade Economy Grade Test Grade

Order Code
9922 157 74111 9922 157 74121 9922 157 74151 9922 157 74131

Defect Specifications
The CCD image sensor can be ordered in a specific quality grade. The grading is defined with the maximum amount of pixel defects, column defects, row defects and cluster defects, in both illuminated and non-illuminated conditions. For detailed grading information, please contact your local DALSA representative.

For More Information
For more detailed information on this and other products, contact your local rep or visit our Web site at http://www.dalsa.com/pi/index.asp

DALSA Professional Imaging
Sales Department High Tech Campus 12a 5656 AE Eindhoven The Netherlands Tel: +31 40 2745110 Fax: +31 40 2743650 www.dalsa.com/pi sales.sensors@dalsa.com

This information is subject to change without notice.

October 30, 2006

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