SRC GRC  University Research Highlights August 2008

SRC GRC University Research Highlights August 2008

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Description: SRC-GRC University Research.

 
Author: Dale Edwards, William Joyner, Kwok Ng, Scott List, Dan Herr, Tim Wooldridge (Fellow) | Visits: 1562 | Page Views: 1567
Domain:  High Tech Category: Semiconductors Subcategory: university research 
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Contents:
Research Highlights for the month of August 2008

Computer Aided Design & Test Sciences
Technical Thrust: Logic & Physical Design
Research Highlight: Cache Model and HDL Implementation for Phase 1 and Report with Plan for Phase 2 Following up on the overall project plan to address the problem of developing power models for the nonmemory portion of the cache subsystem, the research team has designed and have conducted initial investigations into the power consumption of two important cache components: (1) the replacement logic and (2) data cache write buffers. The study reveals that the replacement logic is relatively small and consumes only about 2-3% of the memory power. However, power dissipated in the write buffers is relatively large, and for typical configurations, accounts for at least 1.88 times the memory power. The latter observation validates the initial intuition that models that approximate cache power with only the power due to the memory portion of the cache, could be grossly underestimating the total power. Indian Institute of Technology/Delhi SRC Contact: W. Dale Edwards (Dale.Edwards@src.org) Research Highlight: Final Report Summarizing Research Accomplishments on Variation-Aware Interconnect Modeling and Analysis This is the final project report summarizing research accomplishments and future directions. This project has researched on a number of interconnect modeling and analysis methods considering various process variations. The outcomes of this project consist of two variational interconnect model order reduction methods, one variational waveform-independent driver modeling approach, one parametric interconnect delay/slew analysis method, several parameter reduction methods for handling large number of process variations for digital circuits and one second order statistical static timing analysis method. Texas A&M University SRC Contact: W. Dale Edwards (Dale.Edwards@src.org) Research Highlight: Report on the Demonstration and Testing of Macromodels and Model Interface with an SSTA Tool This report describes two variational modeling techniques that are relevant to interface with an SSTA tool. First, a quadratic timing model characterization methodology is presented. This approach employs statistical parameter reduction methods to efficiently extract quadratic variational logic stage timing models that can be plugged into accurate second-order SSTA. The second technique provides an alternative to full statistical interconnect modeling; it produces a set of design-dependent statistically significant process corners. This offers a trade-off between full statistical modeling and traditional corner based analysis, the latter of which is known to be expensive and pessimistic. Texas A&M University SRC Contact: W. Dale Edwards (Dale.Edwards@src.org) Research Highlight: Modeling Crosstalk in Statistical Static Timing Analysis for Yield Maximization Increasing process variation in the nanometer regime motivates the use of statistical static timing analysis tools for timing verification. As device dimensions get smaller, signal integrity effects such as crosstalk noise become more significant. Therefore, it is necessary to accurately model the impact of crosstalk noise on the circuit delay. Process variations cause variability in the crosstalk alignment which leads to the variability in the delay noise. However, most of the existing approaches model delay noise as a worstwww.src.org GRC is a program of Semiconductor Research Corporation P.O. Box 12053, Research Triangle Park, NC 27709

case deterministic quantity. This work captures the variability of delay noise by first deriving the closedform expressions of mean and standard deviation of the delay noise distribution. Next, the team obtained the correlation information of the delay noise and used it to represent the delay noise distribution in canonical form. Delay noise, in canonical form, can easily be integrated with existing SSTA tools. The authors show experimental results which verify the accuracy of our approach. Univ. of Michigan SRC Contact: W. Dale Edwards (Dale.Edwards@src.org) Research Highlight: Development of Accurate Scalable Equivalent Circuit Models for Multigigahertz Applications This report examines the frequency dependence of substrate coupling admittances. A scalable model for the self admittance suitable for high frequency noise coupling simulations in heavily doped silicon substrates is presented. The cross-coupling admittance can be structurally different depending on the contact geometry and spacing and scalable modeling is not possible. The model is extracted and validated with a high frequency Green's function based solver. A substrate coupling model parameter extraction methodology is also presented. Oregon State University SRC Contact: W. Dale Edwards (Dale.Edwards@src.org) Research Highlight: Report on Validation with Substrate Noise Measurements in a PLL This report examines the effect of substrate noise coupling on the jitter performance of a phase-locked loop and provides validations of simulations with measured data. Oregon State University SRC Contact: W. Dale Edwards (Dale.Edwards@src.org) Research Highlight: Final Report Summarizing Research Accomplishments on Modeling and Analysis for Substrate Noise Mitigation in High Frequency Integrated Circuits The focus of this work has been on an overall design-oriented approach for substrate noise analysis in high frequency mixed-signal ICs. The frequency behavior of substrate coupling for both lightly and heavily doped substrates was investigated using numerical approaches. Numerical tools were developed and enhanced to support model development. Test structures were designed and characterized for substrate coupling at high frequencies and revealed problems and challenges. A scalable model for self admittance for multi-gigahertz frequencies was developed and validated with simulations. Experimental work and validation included noise coupling analysis in low noise amplifiers and phase-locked loops. Oregon State University SRC Contact: W. Dale Edwards (Dale.Edwards@src.org)

Technical Thrust: Test and Testability
Research Highlight: Technical Report on Analysis of Infant Mortality Mechanisms and Their Effects This work uses 90nm transistor-level experimental data, device modeling, and circuit simulations to establish the following results: 1. A transistor with defective gate-oxide, i.e., a gate-oxide early-life failure (ELF) candidate transistor, produces gradually degraded drive currents over time before it completely loses its transistor characteristics; 2. The above phenomenon results in gradual increase in delays of digital circuit paths containing the ELF candidate transistor before the circuit produces functional failures; 3. Gradual delay shifts caused by ELF candidate transistors are large enough to be detected using inexpensive digital techniques. These results can be utilized to overcome scaled-CMOS reliability challenges through ELF identification during production test or on-line during system operation.

Stanford University SRC Contact: William H. Joyner (william.joyner@src.org)

Device Sciences
Technical Thrust: Analog and Mixed Signal
Research Highlight: Characteristics of Sputtered Sm(2)O(3)-SiO(2) MIM Capacitors for Analog IC Applications High performance metal-insulator-metal (MIM) capacitors using sputtered Sm(2)O(3) / PECVD SiO(2) laminate are fabricated and characterized for analog applications where precision is of critical importance. The laminate capacitor can offer high capacitance density, low leakage current and small quadratic voltage coefficient of capacitance (alpha), which can easily satisfy analog IC capacitor density requirements for year 2012 according to the International Technology Roadmap for Semiconductors (ITRS). In addition, effects of constant voltage stress and temperature on leakage current and voltage linearity are comprehensively investigated, and dependences of on frequency and thickness are also demonstrated. Meanwhile, the underlying mechanisms are also discussed. National University of Singapore SRC Contact: Kwok Ng (Kwok.Ng@src.org)

Technical Thrust: Device Sciences Modeling & Simulation
Research Highlight: Electron Mobility: Si, Ge, III-V's with High-k Dielectric (Software Description) The low-field mobility for electrons in low-dimensionality structures (inversion layers, double-gate channels) is calculated using the Kubo-Greenwood formula. Semiconductors considered are Si, Ge, and some III-V compound semiconductors (GaAs, InGaAs). The effective mass approximation is used with nonparabolic corrections. The subband structure is obtained from a 1-D Shroedinger-Poisson solver including Gamma, L, and X valleys. Scattering with bulk phonons (nonpolar and, for III-Vs, also polar), surface roughness and high-k-insulator surface phonons is included. Surface roughness is screened within a multi-subband screening model. Univ. of Massachusetts SRC Contact: Kwok Ng (Kwok.Ng@src.org)

Technical Thrust: Digital CMOS
Research Highlight: Simulations of Atomic and Electronic Structure at the Semiconductor/Dielectric Interface, including Evaluation of Band Offsets This report summarizes computational results for GaAs/Ga(2)O(3) interfaces, aimed at determining the atomic and electronic structure. The establishment of interfacial structure allows determination of band offsets, and forms the basis for investigation of potential defects (and their passivation). The GaAs/Ga(2)O(3) interface is chosen as a prototype for the III-V/oxide interfaces that are of prime interest within the Nonclassical CMOS Center, including InGaAs/Ga(2)O(3). Stanford University SRC Contact: Kwok Ng (Kwok.Ng@src.org) Research Highlight: Report on Device Design and Model-Hardware Comparison for sub 22 nm III-V MOSFETs This report summarizes design studies and modeling of sub 22nm MOSFETs using channels based on

InGaAs and related heterostructures. Electrostatic effects on I-V curves have been quantified. Drain current has been calculated using quasi-ballistic and Monte-Carlo formalisms, and compared with that of Si MOSFETs at various gate lengths. Effects on InGaAs mobility of scattering in high K dielectrics have been calculated. Effects of interface states on C-V curves have been calculated and compared in detail with experimental results of Al(2)O(3)/InGaAs samples from P. McIntyre, B.Shin and E.Kim of Stanford (SRC Non-Classical Research Center). Univ. of California/San Diego SRC Contact: Kwok Ng (Kwok.Ng@src.org) Research Highlight: Ab initio Study of Atomic Structure and Schottky Barrier Height at the GaAs/Ni(0.5)Pt(0.5)Ge Interface The research team reports a study of the atomic and electronic structures of GaAs(001)/NiPtGe(001) interfaces. By using density functional theory, the team studies the dependence of the Schottky barrier on the interface stoichiometry. The calculated p-type Schottky barrier heights vary by as much as 0.18 eV around the average value of 0.5 eV, which corresponds to a strongly pinned interface. The authors relate the As-Ge bonds at the interface with a strong Fermi level pinning. Univ. of Texas/Austin SRC Contact: Kwok Ng (Kwok.Ng@src.org) Research Highlight: The Effect of Annealing on the High-K/Semiconductor Interface The atomic and electronic structure of the high-k amorphous oxide/semiconductor interface is critical to the development of high channel mobility MOSFETs, but selecting the best amorphous oxides for testing is problematic. The structural properties of a-Al(2)O(3)/In(0.5)Ga(0.5)As, a-HfO(2)/In(0.5)Ga(0.5)As, and a-ZrO(2)/In(0.5)Ga(0.5)As interfaces were investigated by density-functional theory (DFT) molecular dynamics (MD) simulations. Realistic oxide samples were generated using a hybrid Classical-DFT MD "melt-and-quench" approach. The interfaces were formed by annealing at 800K (or 1100K) with subsequent cooling and relaxation. This work is distinguished from previous work by the use of amorphous oxide models. Suggestions are made on possible ALD processing improvements. All oxide were tested on the In/Ga-rich In(0.5)Ga(0.5)As(100)-4x2 reconstruction since this surface is resistant to reactions with the oxidants present in ALD reactions Stanford University SRC Contact: Kwok Ng (Kwok.Ng@src.org) Research Highlight: Report on Comparison of Electrical Characteristics, Interface Local Electronic Properties, Band Alignment and DIT of MBE Grown (InGa)(2)O(3)/InGaAs, Gd(2)O(3)/InGaAs, ALDAl(2)O(3)/InGaAs and RE(2)O(3)/InGaAs Heterostructures The dielectrics team of the Ultimate CMOS Center has made several key findings in the past few months: (1) ALD amorphous Al(2)O(3) gate oxide deposition on decapped In(0.5)Ga(0.5)As(001) results in a superior electrical interface. The interface is characterized by an absence of As-O bonds and intermixing. The decapping process is critical for forming the oxide on a clean low defect density surface. (2) MBE growth of amorphous Al(2)O(3) on As-decapped In(0.5)Ga(0.5)As/InP(001) was employed to determine the effectiveness of various growth techniques to achieve a fully oxidized Al(2)O(3) which is critical to lowering defect densities especially oxygen vacancies. (3) Scanning probe studies show that the In/Ga rich reconstruction of In(0.5)Ga(0.5)As(001)-4x2 can be unpinned after MBE gate oxide deposition. This is critical since ALD oxide deposition requires a surface which has low reactivity to oxygen. Synergies: (1) the Taur/Asbeck group is modelling the ALD Al(2)O(3)/InGaAs CV data, (2) the Kummel group is using DFT-MD to model the atomic and electronic structure of the Al(2)O(3)/InGaAs interface, (3) the Rodwell group is planning to MOSFETs with the Al(2)O(3)/InGaAs oxide. Stanford University SRC Contact: Kwok Ng (Kwok.Ng@src.org)

Research Highlight: High Mobility Channels Report This report summarizes ongoing development of high-mobility InGaAs channels for III-V MOSFETs. Previously reported high mobilities (~1000 cm(2)/(V.s) for 1E13/cm(3) electrons in a 5nm channel) were tentatively supported by simple modeling and Hall data. But a subsequent Shubnikov-de Haas technique was not able to distinguish any distinct populations of electrons. To provide experimental verification of these high mobilities, all efforts were shifted to fabrication of working FETs. Channels were redesigned to enable regrowth of contacts, since regrowth on thin InP etch stop layers was rough with unacceptable resistance. Replacing the InP with InGaP produced smooth, epitaxial regrowth with low contact resistance. Univ. of Minnesota SRC Contact: Kwok Ng (Kwok.Ng@src.org) Research Highlight: Chemical Beam Epitaxy (CBE) Report The conditions for selective area epitaxy using chemical beam epitaxy (CBE) were explored. CBE regrowth grew selectively on exposed InGaAs surfaces, but negligible growth occurred on top of patterned SiO(2) masks. Tin doping using tetraethyl tin produced active electron concentrations of 6E19/cm(3), and regrown tin-doped blanket InGaAs contacts to InGaAs showed a contact resistivity of 4.4E-8 ohm-cm(2). In addition, InGaAs surface cleaning techniques developed at UCSB were verified to work for CBE. Removal of native oxides by AsCl(3) damaged the oxides, but cleaning in a hydrogen plasma produced smooth, continuous regrowth. Univ. of Minnesota SRC Contact: Kwok Ng (Kwok.Ng@src.org) Research Highlight: III-V MOSFET Materials Integration Year 2 Executive Summary Fabricating III-V MOSFETs on silicon first requires growth of high quality III-V material on Si. After a slow start in year 1 due to extended CVD tool downtime at Stanford, good progress has been made on this growth. GaAs films on Ge templates on Si showed reasonably low dislocation densities (3-7x10(6) cm(2)) and no antiphase domains detectable by TEM. This has resulted in adequate III-V epitaxy on Si, as reported in the III-V on Ge report. Univ. of Minnesota SRC Contact: Kwok Ng (Kwok.Ng@src.org) Research Highlight: Ge Channels Report Computer simulations of the Ge band states using density functional theory (DFT) have been notoriously poor, since DFT fails for small bandgap materials. A hybrid exchange-correlation functional yields true Ge bandgap in DFT simulations (Kummel group, UCSD). Although the simulation requires three orders of magnitude more resources, it accurately reproduces the Ge (2x4) bandgap, as well as band states arising from the Ge (2x1) reconstruction. These allow simulation not only of band filling and transport, but also interfaces with dielectrics, as discussed in the dielectrics task reports. These are crucial steps toward being able to accurately model Ge channels and interfaces. Univ. of Minnesota SRC Contact: Kwok Ng (Kwok.Ng@src.org) Research Highlight: III-V on Ge Report This report presents the growth of III-V layers on Ge templates on Si. Ge films 2 microns thick were grown on 4-degree (100) miscut Si substrates using multiple cycles of reduced pressure CVD, with pauses for annealing in H(2). GaAs was then grown on the Ge using molecular beam epitaxy (MBE), starting with migration enhanced epitaxy and low temperature growth. Finally, a 10 nm In(0.2)Ga(0.8) As channel was grown, transferred to an ALD chamber, and 8.5nm of Al(2)O(3) deposited to produce a FET with off-state leakage currents
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