Advanced Devices for the End of the ITRS and beyond

Advanced Devices for the End of the ITRS and beyond

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Contents:
2006

Advanced Devices for the End of the ITRS and beyond
Presented by:
Simon Deleonibus Laboratoire Nanodispositifs Electroniques (Electronic Nanodevices Laboratory) CEA/LETI/D�partement NANOTEC(NANOTEC Division) CEA Grenoble 17 rue des Martyrs 38054 Grenoble Cedex France Tel : 33 (0)4 38 78 59 73 Fax: 33 (0)4 38 78 54 59 email: sdeleonibus@cea.fr
� CEA 2006. Tous droits r�serv�s.
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S.Deleonibus LETI/D2NT May 30 2006

1

2006

Nomadic consumer and professional products: biggest market share
Three major product families

� High Performance (HP) t=CV/I � Connection to power network � Low Operating Power (LOP) � Intermittent Nomadic Function � Low Stand-by Power (LSTP) Pstat= VddxIoff � Permanent Nomadic Function Pdyn=CVdd2 f Ptot=Pstat+ Pdyn

� CEA 2006. Tous droits r�serv�s.

Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l'autorisation �crite pr�alable du CEA All rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA

S.Deleonibus LETI/D2NT May 30 2006

2

2006

Nanoscale bulk MOSFET Lg= 15nm
Lg
exte nsio n

gate

Leakage currents and Access resistance are still issues
Gate oxide
(S/m) @ V =50mV
R >>2000 .�m
sd sd

6893 P18

HDD

pockets

d

400

300 60 200

Boron concentration (cm )

G

Scattering by impurities of highly doped short channel
( room temperature)

mmax

msat

(S/m) @ V =1.5V

source

Lm

drain

120

R =1200 .�m

500

Lg~16nm

d

-3

G

100

10 10

18

Si
Gate oxide 17

0 0,01

0,1

L

1

0 10

g

Low field mobility degradation due to halo overlap mostly in the case of efficient SCE control
LETI: G. Bertrand et al., ULIS 2003, SSE 2004

10 10

16

Epi Si (0%C) Si:C 7nm 1.4% 550�C Si:C 7nm 0.3% Si:C Si

Si
15

Gmmax Gmmax

110 120 130 140 150 160 170 180 Depth (nm)

Si:C Dopants Diffusion barrier: Highly Retrograde LETI: T. Ernst et al. VLSI Tech Symposium June 2002, Honolulu profile Strong short channel LETI: T.Ernst et al. VLSI Tech Symposium June 2003, Kyoto effects reduction LETI: F.Ducroquet etal., IEDM, Dec. 2004, San Francisco(CA)
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S.Deleonibus LETI/D2NT May 30 2006

3

2006

Outline
* Introduction *ITRS and linear scaling *Boosters for continued scaling - Metal gate and Hik - Boosting Channel transport * News Device architecture for relaxed scaling
FD SOI & boosted SOI , Multigate, Nanowires

* New materials opportunities on Silicon * Conclusions

� CEA 2006. Tous droits r�serv�s.
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S.Deleonibus LETI/D2NT May 30 2006

4

2006

Ioff vs CV/I
10 1
HP Bulk HP UTB FD

IoffHP bulk(�A/�m) IoffHP DG(�A/�m) IoffHP UTB FD(�A/�m)

Ioff(�A/�m)

0,1 0,01 0,001 0,0001 0,00001

HP DG

MOSFET Static Leakage vs Switching frequency 1/
IsdleaK = Isubl + Ig + Ij (GIDL+BBTL)

High Performance Low Standby Power
LSTP Bulk LSTP UTB FD LSTP DG

IoffLSTP bulk(�A/�m) IoffLSTP UTB FD(�A/�m) IoffLSTP DG(�A/�m)

=CV/I

0,000001
2, 56 1, 97 1, 52 9, 00 E01 1, 17 0, 69 0, 53 0, 41

CV/I(ps)

technology boosters
VDD HP VDD LOP 1.1 0.9 1.0 0.8 1.1 68 25 45 18 0.7 1.0 32 13 23 9 18 7 0.9 0.6 0.8 0.5 0.7 0.7 0.5 1.0 14 5 Source: ITRS 2005
� CEA 2006. Tous droits r�serv�s.

new architectures

VDD LSTP 1.2 1/2pitch(nm) 90 Lg(nm) HP 32

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S.Deleonibus LETI/D2NT May 30 2006

5

2006

Scaling supply voltage
P = Pstat + Pdyn Pstat= VddxIoff and Pdyn=CVdd2 f

Issues to address(trade of Performance & Power): room temperature operation threshold voltage control parasitic effects The most severe constraints are due to(*) : doping concentration fluctuations small volume,asymetry short channel effects low VT vs. VT - low Vsupply Tox thickness,doping concentration, Xj

leakage current in subthreshold regime
even with S=60mV/dec(FDSOI) and VT = 0,20V (Vsupply=0,5V) we will get Ioff = 1nA/�m
(*) much higher impact than thermal fluctuation, energy equipartition, quantum fluctuations S.Deleonibus et al. ESSDERC 1999, Leuven, Sept 1999

tunnel currents SiO2 tunneling dielectric , F-N high doping level
� CEA 2006. Tous droits r�serv�s.
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S.Deleonibus LETI/D2NT May 30 2006

6

2006

Metal gate integration: High K dielectric integration: reduce gate depletion Replacing SiO2 ti = tox i ox capacitance
25 EOT, planar bulk bulk J g, simulated for SiON, planar bulk 20

1.E+03

1.E+02

Tgate

G Cg-depl. Cg-ox Cg-inv. tdepletion tox tinversion D

eletcrode

1.E+01 Jg (A/cm2) EOT, UTB FD EOT, UTB FD 15 EOT (A)

1.E+00

S

1.E-01

10

1.E-02

Jg, limit

for SiON, planar bulk

EOT, DG EOT, DG

5

Cg =

1 1 Cg-ox + 1 Cg-depl
F

1.E-03 High -k needed beyond this High-k beyond this crossover point point 1.E-04 2005 0 2007 2009 2011 2013 2015 2017 2019 Calendar Year

+
-

1 Cg-inv
QB C ox

Tox=1.2nm

Active area(10cm circuit): 1cm
2

2

VT = V FB + 2
VFB = ms -

Pstat(0.5V)= 5W Pstat(1V) = 50W

=> 500W/m2(1/2 AM1) => 5kW/m2

Qox Q = ms - ox Cox Cox

Pstat(1.5V) = 750W !! => 75kW/m2!! (Small Nuclear Power station installed power!!)

MS = M - s
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S.Deleonibus LETI/D2NT May 30 2006

7

2006

TiN/HfO2
Improved leakage/SiO2 Electron Mobility degradation (interface Coulomb scattering)
10 10
3 1

WSix /HfO2
Tuned gate workfunction Improved mobility
10
-4

L =10�m
G

V =+/-1.2V
DS

Jg @ Ivg -VtI = 1V

10 10 10 10

-1

4 decades

SiO2 HfO2

Drain current I

D

HfO2-NMOS HfO2-PMOS SiO2-NMOS SiO2-PMOS

(A)

10

-6

10

-8

200mV 10
-10

-3

WSi /HfO
2 2.7

2 2

WSi /HfO
-5

10
-7

-12

TiN/HfO -0.8

S=60mV/dec 0.8 1.2

2

-1.2
1 1,5 2 EOT(nm)
�eff #1 �eff #2 �eff #3 100 �eff #4 �eff # #5 5 �eff ref SiO2 80 universal 60 �(cm 2/V/s) 40 20

2,5

3

-0.4 0 0.4 Gate voltage V (V)
G

1.3nm

500 (cm�/Vs) 400 300 200 100 0 0 0.1 TiN/SiO

�(cm 2/V/s)

�(cm 2/V/s)

350 300 250 200 150 100 50

+34%

Un ive rsa l

mo b

Electron effective mobility �

eff

ilit y

+20%

WSi /SiO
2 2

2 2 2

2 2

Electrons
6

Holes
6

TiN/HfO

WSi /HfO
2.7

WSi /HfO

nMOS L =10�m
G

0 0 5 5 5 6 0 10 3 10 6 10 9 10 1,2 10 1,5 10 Eeff(V/cm)

0 0 5 5 5 6 0 10 3 10 6 10 9 10 1,2 10 1,5 10 Eeff(V/cm)

0.2 0.3 0.4 0.5 0.6 Effective field E (MV/cm)
eff

0.7

� CEA 2006. Tous droits r�serv�s.

LETI, ST B.Guillaumot et al. IEDM 2002 Dec. 2002, San Francisco(CA) Widiez et al, VLSI-TSA 2006, April 2006, Hsinchu(Taiwan) S.Deleonibus LETI/D2NT May 30 2006

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8

2006

Strain and bandgap engineering
Compressive strain Tensile strain Tensile strain Six Ge1-x Si Si1-y Cy Si Si Six Ge1-x

a= 5.43

Global
pMOS
sSi SiGe 30nm

Band offset and splitting
lh hh (4) (2) hh lh (2) (4)

5.43 Doublegate device -

CHANNEL

GATE BOX
FINFET, Tri Gate FET
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S.Deleonibus LETI/D2NT May 30 2006

15

2006

Planar Double gate by bonding

Simplified Self ALigned and Sized Double active area isolation area gate

IonN(20nm) = 1250 �A/�m IoffN(20nm)= 1.3 �A/�m Lg=20nm M.Vinet et al. IEEE EDL, May 2005
Lg~13nm

Lg~8nm

Poly TiNH fO2S i HfO2 TiN Poly

Hard Mask

IonN(10nm) =1130�A/�m IoffN(10nm)=7�A/�m Lg=10nm

Lg=25 nm
� CEA 2006. Tous droits r�serv�s.
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S.Deleonibus LETI/D2NT May 30 2006

16

2006

Double Gate separation: a flexible device architecture Planar DGMOS From Low Standby Power to High Performance
1.E+011 1.10 1.E+00 1 |Ioff| (�A/�m) 1.E-01-1 1.10 1.E-02-2 1.10 1.E-03-3 1.10 1.E-04-4 1.10 1.E-05-5 Vbg-Vfg 1.10 1.E-06-6 1.10
PMOS DG HP LOP LSTP FD DG HP LOP Vbg-Vfg LSTP NMOS

Drain current (�A/�m)

FD

Vbg

0,16

Vbg

0,14 0,12 0,1 0,08 0,06 0,04 0,02 0

DG mode

Vbg=0.8 to -0.8V

-800

-400

0 400 Ion (�A/�m)

800

1200

0

-0,2

-0,4

-0,6

-0,8

-1

-1,2

Top gate voltage (V)

LETI : M.Vinet et al. SSDM, Sept 2004 Best paper Awards LETI: J.Widiez et al., SOI Conf 2004

- Compact model :1st version available for circuit simulations with independently biasable gates -New design opportunities: SRAM stability and leakage reduction, reduction of number transistors per function(4T SRAM, analog,...)
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S.Deleonibus LETI/D2NT May 30 2006

17

2006

FET Non Planar Multigate
LETI : Jahan et al, VLSI Tech Symposium, June 2005 Kyoto(Japan)

Functional N-Fets tested down to Lg=10 nm
Lg = 10 nm
1E-03 1E-04 1E-05 ID (A/�m)
VD=0.1V VD=1.2V

TiN

HfO2

1E-06 1E-07 1E-08 1E-09 1E-10 -0.2 0 0.2 0.4 0.6 0.8 VG (V) 1 1.2 NMOS Lg=10 nm WFIN=50 nm

Si
TEM cross-section of a 60 nm silicon finger fet device

NMOS: ION=326�A/�m, IOFF=600pA/�m @ VD=1.2V, SS=90mV/dec, DIBL=130mV

Excellent ION/IOFF ratio of 5.105 for a 10 nm non planar device and very good channel control
S.Deleonibus LETI/D2NT May 30 2006

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18

2006

sSOI(FET like devices): length and width effect
� Mechanical Simulations done
yy
Enhancement (%)
40

to understand the gain decrease (MESA isolation).

30

Large devices FD sSOI (this work) FD sSOI PD sSOI or SGOI sSi/SiGe

[8] sSi/SiGe

This work
20

[4]

FD sSOI

[7] FD sSOI [11] PD SGOI

xx

[12] sSi/SiGe [9] sSi/SiGe [7] FD sSOI [5] PD sSOI [10] PD SGOI

10

BOX
140 120 100 80 60 40 20 0 0.01
0 100 200
Theor. mobility Exp. g
m,max

I
0 0

ON

20

Gate Length (nm)

40

60

80

100

L =10�m

x sSOI (a)
xx xx (MPa) (MPa)

Buried oxide

~0.1�m

g

m,max

(S)

y z

Enhancement (%)

10

-6

G

V =0.05V
D

SOI sSOI

+65%

1500 1000 500 0

10

-7

+40%

0.1

1

10

(b)

x (nm)

x (nm)

300

400

500

600

Width (�m)

10

Width (nm)

100

1000

LETI: F. Andrieu et al., VLSI Tech Symp, 2006

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Width: evidence of a change from a bi-axial strain into an uni-axial strain
S.Deleonibus LETI/D2NT May 30 2006

� CEA 2006. Tous droits r�serv�s.

19

2006

Silicon On Insulator based architectures Subthreshold regime � optimizing electrostatics
� Subthreshold regime is limited to 60mV/decade at 300K
L

Planar Fully Depleted SOI
tSi

SiO2

Si

Ratio : tsi/L x 1/4

Planar Double-gate, FinFET
gate SiO2

Tri-gate Surrounding-gate (nanowire)
SiO2

X 1/2

Film thickness tSi required for a given L value
B.Doyle � VLSI'03 10A-2, 2003 M. Ieong et al. Science vol. 306 Dec. 2004 * No direct S-D tunnel introduced ...

SiO2

Si

x1 X 1-2
Si
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S.Deleonibus LETI/D2NT May 30 2006

20

2006

Ultimate transport properties in Si Ballistic transport (Planar DGMOS)
Quasi-ballistic model

I DS

0.35 0.3 0.25 0.2 0.15 40 80 LG=10nm LG=20nm LG=70nm

1- r = WCOX (VGS - VT ) inj 1+ r
* Decrease of the rSAT coefficient at low temperatures * Increase of LG Increase of rSAT
T Thermionic herm ioniccom ponent Ballistic
current current

LETI: Barral et al, ULIS 2006
120

T Tunnelingponent Diffusive unnelingcom

B allisticcurrent and

Transport

T (K)

160

200

240

280

Initial injection velocity at source Reflexion on ionized dopants(channel or drain) Interface roughness will reduce ballisticity
G.Bertrand et al SNW2000 Honolulu(HI), ULIS2003Munchen(FRG)

Energysubbandi V alleyj

y

x

new source architectures: electrostatics and material

he echa Figure 1. 2-D potential energy distribution in the channel. T essential m governingthecarriertransm issionarealsoillustrated. � CEA 2006. Tous droits r�serv�s.
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2006

Opportunities for other materials on Silicon
�n (cm2V-1s-1) �p (cm2V-1s-1) th (W/m/K) Rel. K Eg(eV) Vsat(107cm/s)

Material

Si

Well established high quality material (>40yrs experience) Oxidizable !

1400

500 1900 400 1800 750
LETI:

141 59.9 46 >1500 Highest _

11.9 16 12.5 5.7

1.12

0,86

GeSilicon compatible 3900
Available in all fabs

0.66 0,60 1.42 0,72 5.47 2,7 0.16 5,0

GaAs

8900

Opto Power RF applications Ge compatible

C-Diamond 1800 Passive layer
/graphite

combine w BOxMost (thermal shunt)

compact logic

th

High short channel effect immunity

InSb

78000

16.8

Highest �n but Worst �n/�p!!
S.Deleonibus, ICSICT 2004, Beijing, Oct. 2004 , S.Deleonibus et al., Int.Journ. High Speed Electronics, March 2006 S.Deleonibus LETI/D2NT May 30 2006
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22

2006

Future devices: GeOI on Silicon Substrate
GeOI pMOS w. HfO2+TiN gate stack
/Vs)
2 GeOI S-SOI

Processed 200mm GeOI

Electron mobility (cm

1000 900 800 700 600 500 400 300
Exp. (Rim et al.)

SOI model

200 12 10

Ge mobility (Monaco)

Inversion charge (cm )

-2

10

13

1000

100

Jd (�A/�m) @ Vd=-1,5V et Vg-Vt=-2V

CEA-L�ti
Ge bulk - Stanford (IEDM 02) 10 Ge bulk - MIT (IEDM 03) GeOI IMEC (2004 non publi�) Ge bulk - IBM (IEDM 04) GeOI - Nat. Chiao Tung Univ. (EDL 04) 1 100 1000 Lg (nm) 10000 100000

CTRIM simulation SIMS measurements
L. Clavelier et al, Silicon Nano Workshop, ,Kyoto 2005
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S.Deleonibus LETI/D2NT May 30 2006

23

2006

Future devices: Substrate engineering

� Main development on Buried oxide to manage heating issues:

SOI thickness (nm)
S.Deleonibus et al. , Int. Journ. of High Speed Electronics, March 2006

� Suppress self heating: Replace the buried oxide by materials with higher thermal conductivity Best candidate: Diamond (better than Bulk-Si). Available within CEA: Strong background on diamond growth and bonding
S.Deleonibus LETI/D2NT May 30 2006

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24

2006

Perspectives: Nanoelectronics CMOS devices
poly SiON metal high k

gate stack

electrostatic cntrol

bulk

thermal

planar
PDSOI MuGFET MuCFET ...

3D

� � �

Scaling can be foreseen down to Lg=5nm. Nanoelectronics Base platform Power consumption: major issue (sub 1V supply voltage). => Device/ system architecture optimization

ADD substrate engineering

�?

strain

ADD High � material

`07 65nm

`09 45nm

`12 32nm

`15 22nm

FDSOI: Advanced substrate (BOX, stressors, thermal shunts,...) Dual strained channels(GeOI option); Dual metal gates (Hi Perf); Metallic S&D (Schottky vs ohmic cts)

New routes (LETI playground)

New device architectures: Max Ion/Ioff and Low Power Multigate, Multichannels, Innovatives architectures,...
3D integration: elementary function New SOC concepts(analog, RF, Hi Perf,Memories): � CEA 2006. Tous compound SC/OI/Si based substrate, molecular droits r�serv�s. electronics, ...
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2006

Thank you for your attention
Acknowledgements Olivier Faynot, Thomas Ernst, Thierry Poiroux, Maud Vinet, Laurent Clavelier, Cyrille Leroyer, Sylvain Barraud, Jean Charles Barb�, Emmanuel Hadji

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