28nm FD - SOI I ndustrial S olution

28nm FD - SOI I ndustrial S olution

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Description: "28nm FD-SOI Industrial Solution - Overview of Silicon Proven Key Benefits. FDSOI/UTBB Technology Benefits, FDSOI Complete Solution. Demonstrated Reduced design effort for Full SoC porting.

Same design flow as for 32/28nm LP •Same tools used •Same design cycle time. Direct mapping of IPs + ECO •Script based •Faster than rerunning synthesis •Floorplan reuse. True concurrent engineering •FDSOI product received before bulk version.

28FD Proven Excellent Core Energy efficiency. Same Perfs as 28LP with 200mV Less. SoC Cooler Demo.

SOC Design, Design Solutions, Silicon Technologies. 28FD Devices Portfolio. Design Platform extended IP offer-Improved Memory Minimum Voltage.

Vmin gain thanks to better mismatch on FDSOI devices (undoped channel) Design and Ips EcoSystem•Conventional (bulk) design flow •Cadence, Mentor, Synopsys, •Apache, Atrenta. 4-terminals spice models available, from PSP •Major simulators supported : Hspice, Eldo, Spectre •Same low power design techniques than bulk. In addition : •Optimized power switches •Extended poly-bias •Reverse & forward Dynamic body bias •Digital IP suppliers ecosystem in place Synopsys, Cadence, ARM, ...•Phys IP suppliers ecosystem : wide IP offering •ST Technology R&D, ST divisions •Cadence, eSilicon, Evatronics...•Universities and research institutes •access to 28FDSOI for prototyping and small series-CMP in Grenoble (site cmp.imag.fr)-link to CMP through VDEC in Japan, and CMC in Canada.

28nm Planar UTBB FD -SOI Roadmap. ST DESIGN PLATFOR ...Please navigate Paper pages for more details.

 
Author: Laurent Le Pailleur (Fellow) | Visits: 2761 | Page Views: 3433
Domain:  High Tech Category: Semiconductors Subcategory: Transistors 
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Contents:
28nm FD-SOI Industrial Solution:
Overview of Silicon Proven Key Benefits

Laurent LE PAILLEUR

28nm FDSOI Technology Line Management
Technology R&D – Crolles - France

FDSOI/UTBB Technology Benefits
Ultra thin Body & Box

UTBB

Bulk Planar

Front Gate

Gate
GND

VDD

GND

VDD

Gate

Gate
Source

Drain

Drain

Source
Thin Box

Punch
Through !

Substrate

Substrate

Back Gate

Electrostatic issues
 High Sub-VT slope
 High DIBL

Electrostatic Recovery
Low Sub-VT slope
 Low DIBL

Electrostatic issues
 Low Body Biasing Efficiency

Back Gate Biasing scheme
 High Body Biasing Efficiency

28nm FDSOI Industrial Solution : Silicon Proven Key Benefits

L. Le Pailleur – SOI Consortium – Kyoto, June 2013

2

FDSOI Complete Solution
3

IPs
Libraries

Analog / RF
Low power
Cad Flow

Performances
Roadmap

Packaging

Multi-Sourcing

Qual’d solution
Manufacturing

28nm FDSOI Industrial Solution : Silicon Proven Key Benefits

L. Le Pailleur – SOI Consortium – Kyoto, June 2013

Demonstrated Reduced design effort
for Full SoC porting
• Same design flow as for 32/28nm LP
• Same tools used
• Same design cycle time

• Direct mapping of IPs + ECO
• Script based
• Faster than rerunning synthesis

• Floorplan reuse

• True concurrent engineering
• FDSOI product received before bulk version

CPU
Dual Cortex A9

GPU
SGX544 MP1

+40% in speed

+20% at nom V

> 3X at low V

Power reduction

HD camera
IP

+30% in speed

PLLs
Up to 4.6GHz

LPDDR2
533Mhz

-15% in power

-15% in power
28nm FDSOI Industrial Solution : Silicon Proven Key Benefits

L. Le Pailleur – SOI Consortium – Kyoto, June 2013

4

Performances

28FD Proven Excellent Core Energy efficiency

Same Perfs as 28LP
with 200mV Less
-400mV with 1.3V FBB

Hit 3GHz
Target

>80% extra speed @ 1.3V FBB

1GHz with FD-SOI

28nm FDSOI Industrial Solution : Silicon Proven Key Benefits

L. Le Pailleur – SOI Consortium – Kyoto, June 2013

5

Low Power

SoC Cooler Demo

28nm FDSOI Industrial Solution : Silicon Proven Key Benefits

L. Le Pailleur – SOI Consortium – Kyoto, June 2013

6

Complete solution

Design Platforms
Foundation
Libraries
Digital Logic
Cells

Clock
Generators

CAD Kits

Data
Converters

Design
Methodologies

Embedded
Memories

Interfaces
PHY

Modeling & CAD
Views Generation

Testability &
Repair Solutions

Design Solutions

Design
Methodologies

IOs
& Fuse

SOC Design

Analog & Mixed
Signal IPs

RF & Power
Management IPs

Si Validation &
Qualification

Silicon
Technologies

Pilot SOC Projects
ARM CPUs, GPUs Implementation
IP Services, Support & Training

28nm FDSOI Industrial Solution : Silicon Proven Key Benefits

L. Le Pailleur – SOI Consortium – Kyoto, June 2013

7

Devices

28FD Devices Portfolio
8

MOSFETs devices

Analog devices

Thin oxide transistors suite:
SG NMOS (Vddnom=1V) RVT & LVT
SG PMOS (Vddnom=1V) RVT Free !
& LVT
Thick oxide transistors suite:
EG NMOS (Vddnom=1.8V) RVT & LVT
EG PMOS (Vddnom=1.8V) RVT & LVT
EGV NMOS (Vddnom=1.5V) RVT & LVT
EGV PMOS (Vddnom=1.5V) RVT & LVT
Power switch (EG PMOS RVT)

Vertical bipolar device (PNP)
Varactor capacitance EG N/PCAP
MoM capacitor / 2fF/um2 min pitch
Resistances suite:
P+ poly unsilicided R
P+ poly unsilicded high precision R
N+ diffusion unsilicided R
N well R

ESD devices
STI diodes / N+ on Pwell and P+ on Nwell
Transistors suite:
Unsilicided EG NMOS on bulk (RVT)
Unsilicided SG NMOS on bulk (RVT)
Unsilicded SG NMOS on SOI (RVT/LVT)

Devices break-down

SRAM devices
HD cell / Single Port 0.120um2
HS cell / Single Port 0.152um2
LV cell / Single Port 0.197um2
RF cell / Dual Port 0.298um2

Device Type
MOSFET
SRAM

Cell capacitance / SG oxide on SOI
Drift transistor / EG NMOS RVT

All bit-cells (SP/DP/RF)
OTP cell

Drift transistor

EG NMOS

Vertical Bipolar

PNP

Varactors

Decoupling devices
MiM capacitance /

20fF/um2

Resistors
with Ta2O5

BULK part

All transistors (SG/EG)

OTP capacitance

OTP devices

SOI part

EG NCAP
P+ Poly (on FO)

Diodes suite
ESD Devices

28nm FDSOI Industrial Solution : Silicon Proven Key Benefits

N+ diffusion / N well
N+/Pw & P+/Nw

SG/EG NMOS

SG NMOS

L. Le Pailleur – SOI Consortium – Kyoto, June 2013

Libraries

Design Platform extended IP offer

28nm FDSOI Industrial Solution : Silicon Proven Key Benefits

L. Le Pailleur – SOI Consortium – Kyoto, June 2013

9

Libraries

Improved Memory Minimum Voltage

AVt (mV.µm)

Vnom

Vddmin
-100mV

3

Vddmin 28LP

Vddmin 28FDSOI

Probability (%)

Vddmin on 0.120µm² bitcell

2.5

Mismatch
-40% on
FDSOI vs. LP

2

1.5

1

Vddmin (V)

Pass
Gate

Pull
Down
LP

Pass
Gate

Pull
Down

FDSOI

Vmin gain thanks to better mismatch on FDSOI devices (undoped channel)

28nm FDSOI Industrial Solution : Silicon Proven Key Benefits

L. Le Pailleur – SOI Consortium – Kyoto, June 2013

10

Design Platform

Design and Ips EcoSystem

• Conventional (bulk) design flow

11

• Cadence, Mentor, Synopsys,
• Apache, Atrenta

• 4-terminals spice models available, from PSP
• Major simulators supported : Hspice, Eldo, Spectre

Prototyping

Floorplan Finalization

• Same low power design techniques than bulk.
In addition :

Physical Implementation

SignOff

Low Power Digital Design Flow

• Optimized power switches
• Extended poly-bias
• Reverse & forward Dynamic body bias

• Digital IP suppliers ecosystem in place
Synopsys, Cadence, ARM, …

• Phys IP suppliers ecosystem : wide IP offering
• ST Technology R&D, ST divisions
• Cadence, eSilicon, Evatronics…

• Universities and research institutes
• access to 28FDSOI for prototyping and small series
- CMP in Grenoble (site cmp.imag.fr)
- link to CMP through VDEC in Japan, and CMC in Canada
28nm FDSOI Industrial Solution : Silicon Proven Key Benefits

Adaptive Voltage
Scaling

Dynamic Voltage
& Frequency
Scaling

Power / Clock
Gating

Process
Monitoring &
Compensation

Power
Switches

RTL Power
Estimation

Multi Vt
Capabilities

Reverse &
Forward
Body Bias

L. Le Pailleur – SOI Consortium – Kyoto, June 2013

Manufacturing

28nm Planar UTBB FD-SOI Roadmap
2011
Q3

2012

Q4

Q1

Dev. reticle

Q2

2013

Q3

Proc. Qual.

Q4

Q1

Q2

2014

Q3

Q4

Q1

PDK Si based

PDK prod.

DP 2.0 BE

AVAILABLE FOR
PRODUCTION
Has reached “open for risk
production” milestone

DP 3.0

Design platform
1st SoC PG

Q4

Technology is

Design enablement
DP 1.0 FE

Q3

Ready for risk prod.

Process dev. & qualification @ Crolles
PDK eval.

Q2

MPW1

MPW2

MPW3

MPW4

MPW5

MPW6

MPW7

Prototype service @ Crolles
SoC demo @ CES

ST DESIGN PLATFORM
IS AVAILABLE

Risk production @ ST
2nd source enablement @ GF

SOITEC, SEH, MEMC
FDSOI wafers recognized providers
28nm FDSOI Industrial Solution : Silicon Proven Key Benefits

L. Le Pailleur – SOI Consortium – Kyoto, June 2013

12

Long Term Solution

Planar UTBB FD-SOI
Enabling Moore’s Law with Planar Process & Design
28nm FDSOI

14nm FDSOI

10nm FDSOI
0.9V
113CPP
90Mx
0.8V
90CPP
64Mx

AVAILABLE
TODAY!

2012

0.7V
64CPP
48Mx

TODAY IN
DEVELOPMENT

2013

2014

2015

2016
TODAY IN
R&D

28nm FDSOI Industrial Solution : Silicon Proven Key Benefits

L. Le Pailleur – SOI Consortium – Kyoto, June 2013

13

Long Term Solution

FDSOI Technology Road-Map
and Process Boosters
Boosted
back bias

Performance

10nm
FD-SOI

µ boost

at same Vdd

+30%

Raccess
2nd gen RSD
+ cSiGe
sSOI
Vt and
µboost

14nm
FD-SOI

at same Vdd

+40%

Racces

28nm
FD-SOI

15nm
TBOX

In situ
doped RSD

SiGe
channel
for PFET
Dual Epi S/D
L=20nm

A
s

A
s

ISD Si S/D
Tsi=7nm

20 nm BOX

28nm FDSOI Industrial Solution : Silicon Proven Key Benefits

L. Le Pailleur – SOI Consortium – Kyoto, June 2013

14

14nm R&D

14FDSOI Technology Features
High Performance Logic
14FDSOI offer

NFET







High performance, low power applications
Thin oxide devices : 2-Vts, poly biasing & FBB
Thick oxide devices : 2-Vts, multi voltage support
6T-SRAM bitcells:0.081um2, 0.089 um², 0.107um2
Full suite of passive devices including high
precision MOL resistor and MIM cap

14FDSOI process features

PFET












UTBB substrate (BOx 20nm Si 6nm)
Hybridation (Mix SOI & bulk) for analogue
Si/SiGe channels for N & P
Gate first HK (HfO2) integration
Dual epi SiCP/ SiGeB for transistor boost
NiSi
Local interconnect for standard cells density
90nm CPP, 64nm Mx
Up to 11 Cu metal levels
8 masks less than 20LPM for +20% speed @0.9V

28nm FDSOI Industrial Solution : Silicon Proven Key Benefits

L. Le Pailleur – SOI Consortium – Kyoto, June 2013

15

Conclusions
• ST FD-SOI technology
• 28nm FD-SOI ready for production with Compelling silicon results obtained
• Full Design Platform available with silicon-qualified extended range of IPs and Phys
• ST next gen consumer products in FD-SOI

• FDSOI Key benefits
• Best Speed / Power performances ever, covering full spectrum from LP to HP
• Right value for money : no complex G stressors, same equipment as bulk planar

• Worldwide UTBB FD-SOI eco-system
• enabled ST to go from concept to right first time SoC demonstration
• Ecosystem further expanding with new manufacturing partners and IP providers

• FD-SOI technology: scalable
• Roadmap down to 10nm, with 14nm node in development

28nm FDSOI Industrial Solution : Silicon Proven Key Benefits

L. Le Pailleur – SOI Consortium – Kyoto, June 2013

16

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