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A 16nm 256-bit Wide 89.6GByte/s Total Bandwidth In-Package Interconnect with 0.3V Swing and 0.062pJ/bit Power in InFO Package

 Mu-Shan Lin, Chien-Chun Tsai, Cheng-Hsiang Hsieh, Wen-Hung Huang, Yu-Chi Chen, Shu-Chun Yang, Chin-M
  15th-Nov-2016
Description: In Package Memory (IPM): Additional memory hierarchy between on-chip SRAM and off-chip DDR- Smaller capacity; higher bandwidth; faster latency; Advantages- DRAM is more cost-effective than eDRAM, Non-TSV allows fine pitch RDL and shorten trace between AP and IPM, Short trace enable termination-less IO design. Advanced Package Solutions: Why we choose FO-WLP? Ultra-fine pitch RDL (W/S < 5um/5um), Ultra-thin package (~0.6mm including BGA), Smaller die size (no-TSV), Suit for smartphones, tablets, and wearables.
Views: 1652
Domain: Electronics
Category: Semiconductors
Contributing Organization: Hot Chips
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Contents:
A 16nm 256-bit Wide 89.6GByte/s Total Bandwidth
In-Package Interconnect with 0.3V Swing and
0.062pJ/bit Power in InFO Package
Mu-Shan Lin, Chien-Chun Tsai, Cheng-Hsiang Hsieh,
Wen-Hung Huang, Yu-Chi Chen, Shu-Chun Yang, ChinMing Fu, Hao-Jie Zhan, Jinn-Yeh Chien, Shao-Yu Li, Y.-H.
Chen, C.-C. Kuo, Shih-Peng Tai and Kazuyoshi Yamada

Taiwan Semiconductor
Manufacturing Company, Ltd.
DTP
Taiwan
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