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BEOL Wiring Process for CMOS Logic

 G. Dan Hutcheson
Description: This paper was written to provide a formal technical definition of the emerging terms BEOL, FEOL, and intermetal dielectric at a time when multilevel, planarized interconnect was just emerging in semiconductor manufacturing. It was based on a compilation of roadmaps from the largest chip makers around world. Terminology varied substantially among them, and I had been asked to sort them out. It was critical for equipment makers, because they struggling to keep up with the demands of chip makers. Device speeds, sale, and dimensions were pushing new materials such as copper and low k dielectrics. While it was first published in 1995, much of it is still relevant today. It is also interesting to see what we see as easy today seen as almost impossible yesterday. It is a testament to the amazing ingenuity of the people who work in semiconductors and lends confidence to their ability to solve them in the future.
Views: 5121
Domain: Electronics
Category: Semiconductors
Contributing Organization: VLSIresearch
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