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Design for Test at RTL and Achieve Early Design Closure

 Atrenta
  14th-Aug-2007
Views: 2281
Domain: Electronics
Category: Semiconductors
Contents:
THINK

SpyGlass-DFT

TM

Design for Test at RTL and Achieve Early Design Closure

THINK

With the rapidly soaring cost of silicon especially at 130nm and below, testability of designs is becoming a key aspect of design closure. While there are tools that address test issues at gate-level or test equipment for silicon, achieving high test coverage entails designing for test. Atrentas SpyGlass-DFT i ... See more

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