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Design with Test

 Cadence
  14th-Aug-2007
Views: 1954
Domain: Electronics
Category: Semiconductors
Contents:
W H I T E PA P E R

DESIGN WITH TEST

bAckGRouND
As process geometries shrink to 65nm and below, manufacturing test must expand its role in the design, implementation and production of semiconductor devices. Much like DFM and its manufacturing-driven design flow, which is an accepted requirement today, a "test-driven" design and implementation flow is now at the forefront of chip design concerns. ... See more
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09 January, 2009