weSRCH App on Apple
Freescale Semiconductor Inc. has developed a form of packaging that combines several die – either bare or packaged – in modules that are smaller and, perhaps, less costly and higher performing than traditional packaged chips.
Redistributed Chip Packaging (RCP) takes bare die as well as off-the-shelf packaged parts -- memories, for example -- and glues them in position on a 300-mm panel.
For a wireless phone, the dice might include a transceiver done in RF-CMOS, a baseband/applications processor made in CMOS, a power amplifier fabbed in GaAs, bare or packaged memories, and a power management/user interface controller, plus discretes.
Once multiple combinations of these die are placed on the panel, epoxy and molding compound are applied, and connection patterns are lithographically defined, using low-cost masks. Vias are etched through a dielectric to the chip's I/O pad contacts, and copper or aluminum interconnects are electroplated.
The photolithography, etch and plating steps result in one or two interconnect levels on both the top – for connections to the die -- and bottom, for linking to the system substrate with either land grid arrays or C5 balls.
Karl Johnson, director of Freescale’s Tempe, Arizona research laboratory, said a pilot line is nearly completed which could be used for low-volume commercial production early in 2008. A high-volume facility is planned for “somewhere in Asia” that would go into production late in 2008. Freescale hopes to create a network of assembly subcontractors that could implement RCP, and is willing to license the technology to other chip vendors.
 
The approach recently passed moisture, thermal cycling, and stress tests.
By eliminating the bond pads and chip package substrate, the module area is reduced by about one-third, including in the Z dimension. Performance gains are available, particularly if the chip’s IO is redistributed away from the periphery. A redesign of the IO would “reduce the length of the lines and greatly reduce parasitics, improving the performance of the products,” Johnson said, adding that “the process is very compatible with using thermal mold compounds or heat shields.” 
“We are doing out due diligence, making sure it is a solid technology once it is released. Right now we are planning on sampling at the end of this year to key customers, and based on that we may go into limited production here at Tempe early in 2008,” Johnson said. 
Extensive wafer probes are needed to ensure that known good die (KGD) are used to make the multi-chip modules. “Excellent yields are needed for the starting dice,” he said.
Another challenge is to maintain alignment of the chips as they are positioned on the panel, and to control stressors on the material.
“In the panel, we need to have excellent control of die. In our lab we are aligning to pads with a 130-micron pitch. That is with mechanical kinds of alignment. When we get all of our equipment together, we can get to 60-70 micron alignments, which is comparable to the pitch dimensions one sees in leading-edge wirebonds,” Johnson said.
Tomorrow: RCP supports Freescale’s wireless chipset strategy
Next

Freescale RCP packaging moving towards early production

  1879      Nov 30, -0001
Freescale Semiconductor Inc. has developed a form of packaging that combines several die – either bare or packaged – in modules that are smaller and, perhaps, less costly and higher performing than traditional packaged chips.
Redistributed Chip Packaging (RCP) takes bare die as well as off-the-shelf packaged parts -- memories, for example -- and glues them in position on a 300-mm panel.
For a wireless phone, the dice might include a transceiver done in RF-CMOS, a baseband/applications processor made in CMOS, a power amplifier fabbed in GaAs, bare or packaged memories, and a power management/user interface controller, plus discretes.
Once multiple combinations of these die are placed on the panel, epoxy and molding compound are applied, and connection patterns are lithographically defined, using low-cost masks. Vias are etched through a dielectric to the chip's I/O pad contacts, and copper or aluminum interconnects are electroplated.
The photolithography, etch and plating steps result in one or two interconnect levels on both the top – for connections to the die -- and bottom, for linking to the system substrate with either land grid arrays or C5 balls.
Karl Johnson, director of Freescale’s Tempe, Arizona research laboratory, said a pilot line is nearly completed which could be used for low-volume commercial production early in 2008. A high-volume facility is planned for “somewhere in Asia” that would go into production late in 2008. Freescale hopes to create a network of assembly subcontractors that could implement RCP, and is willing to license the technology to other chip vendors.
 
The approach recently passed moisture, thermal cycling, and stress tests.
By eliminating the bond pads and chip package substrate, the module area is reduced by about one-third, including in the Z dimension. Performance gains are available, particularly if the chip’s IO is redistributed away from the periphery. A redesign of the IO would “reduce the length of the lines and greatly reduce parasitics, improving the performance of the products,” Johnson said, adding that “the process is very compatible with using thermal mold compounds or heat shields.” 
“We are doing out due diligence, making sure it is a solid technology once it is released. Right now we are planning on sampling at the end of this year to key customers, and based on that we may go into limited production here at Tempe early in 2008,” Johnson said. 
Extensive wafer probes are needed to ensure that known good die (KGD) are used to make the multi-chip modules. “Excellent yields are needed for the starting dice,” he said.
Another challenge is to maintain alignment of the chips as they are positioned on the panel, and to control stressors on the material.
“In the panel, we need to have excellent control of die. In our lab we are aligning to pads with a 130-micron pitch. That is with mechanical kinds of alignment. When we get all of our equipment together, we can get to 60-70 micron alignments, which is comparable to the pitch dimensions one sees in leading-edge wirebonds,” Johnson said.
Tomorrow: RCP supports Freescale’s wireless chipset strategy
About weVISION: weQuest's are written by G Dan Hutcheson, his career spans more than thirty years, in which he became a well-known as a visionary for helping companies make businesses out of technology. This includes hundreds of successful programs involving product development, positioning, and launch in Semiconductor, Technology, Medicine, Energy, Business, High Tech, Enviorntment, Electronics, healthcare and Business devisions.

You may like this also:

...
20 September, 2019
...
19 September, 2019
...
18 September, 2019
Jim Ryan
17 September, 2019

Huawei's Vision on AI By Jason WU

Here mention the Huawei’s vision on AI including with intelligent cloud services, pervasive & trustworthy. Also, include the Huawei partnership drives growth in B2B.

Jason WU
16 September, 2019
Andrea Lati
13 September, 2019
Diogo Avelino
13 September, 2019
...
12 September, 2019
weSRCH App on Apple

Recent weVISIONs

Open IC Design Platforms ... with Michael Wishart of Efabless
Michael WishartEfabless
20 August, 2019
Tom Caulfield on what's next at GLOBALFOUNDRIES
Tom CaulfieldGLOBALFOUNDRIES
22 July, 2019