The chip industry is on the front edge of a major transition to high-k dielectrics with metal gate electrodes, and the 2007 Symposium on VLSI Technology is the first major technology conference to come along following the January high-k announcements by Intel, IBM, NEC, Sematech, and others.
And it’s not all logic. Samsung Electronics researchers will go to the VLSI symposium (June 12-14 in Kyoto) with a DRAM process which integrates a hafnium-silicon-oxygen-nitrogen (HfSiON) gate dielectric. According to an abstract of the Samsung paper, the high-k gate dielectric reduced the gate leakage, and, surprisingly, delivered better mobility than plasma nitrided oxide. The improvements claimed by Samsung are significant: a 22 percent better propagation delay; one order of magnitude lower standby current; and a doubling of the data retention time.
Qimonda researchers will go from Dresden, Germany to Kyoto to discuss their research into using carbon in the electrodes of the DRAM cell capacitors. DRAMs with sub-40-nm design rules, using high-k trench capacitors and carbon-based electrodes, show improved serial resistance, capacitance, leakage, reliability, and temperature stability, according to the abstract of the Qimonda paper.
The Samsung and Qimonda papers show avenues for DRAM performance improvement at a time when the memory workhorse is facing its own set of scaling challenges.
NEC Electronics has a 45-nm low-power, low-standby-power CMOS platform which includes a polysilicon electrode and a hafnium SiON dielectric, with varying thicknesses for the SiON layer. The paper’s abstract describes way to share the ion implant steps among the core logic and I/O transistors, while suppressing the reverse narrow channel effect.
Sematech researchers will look at the problems posed by the PMOS transistors when high-k dielectrics are introduced, where thermal instability and fluctuating threshold voltages have bedeviled the high-k introduction for several years. At the VLSI symposium, Sematech researchers will describe a dual-channel scheme, with a lanthanum oxide (La2O3) cap for the NMOS transistors and a SiGe-enhanced channel in the PMOS devices. The strained SiGe-on-silicon channel resulted in a reduction of the threshold voltage by as much as 300 milliVolts.
IMEC researchers continue their pursuit of a nickel FUSI (fully silicided) approach to forming the metal gates on a hafnium silicate dielectric. The abstract of the paper suggests that FUSI is ready for manufacturing at the 45-nm and 32-nm nodes, with “excellent EOT scalability and no PMOS voltage flat band rolloff down to an EOT of 7 Angstroms.”
In the plenary session, IMEC will describe a FUSI process than introduces a Dysprosium oxide (DyO) cap layer on both HFSiON and SiON dielectrics. The 5 Angstrom DyO cap layer can lower the nFET threshold voltage by 300 milliVolts on the hafnium dielectric, and even more with a plasma-nitrided oxide. The abstract promises a demonstration of a DyO cap layer selective removal process, pointing the way toward a low-threshold-voltage CMOS process.