This year’s tenth International Interconnect Technology Conference (IITC), planned for early June at the San Francisco airport, comes 10 years after IBM and Motorola researchers announced plans to use copper interconnects. A decade of chemical-mechanical polishing later, the chip industry is looking at several ways to extend the reach of copper/porous low-k interconnects to the 32-nm node.
Interestingly, a look at the paper abstracts shows that many of the more interesting papers this year are from Japanese companies. Fujitsu has a paper on nano-clustering silicon (NCS) dielectrics, which were tested on 45-nm test structures. Creating thin barrier layers and using the NCS dielectrics, the Fujitsu researchers claimed an 86 percent reduction in resistance-capacitance delays.
Researchers from Sony and Toshiba will go to the IITC with separate papers on hybrid dual-dielectric schemes, which put one dielectric at the bottom of the vias, and the other at the top. These processes also form the barrier and copper seed layers in one step, and could reduce process complexity.
Sony used a manganese oxide barrier layer with lower resistance than tantalum. MnO has several other benefits: fewer stress-induced voids, longer electromigration lifetime, and no pore-sealing process. These self-formed barrier layers do not adhere at the bottom of the vias, which reduces resistance.
The Sony researchers combined an MnO barrier with a copper-silver alloy for the metal lines, and found advantages, compared with the conventional tantalum barrier layer with copper for the 32-nm back end of the line.
A paper from NEC also looks at the barrier layer challenge, replacing tantalum with a ruthenium/tantalum nitride liner. Copper can be plated directly on ruthenium without creating an interface layer between the two, reducing complexity.
IBM researchers will go to the IITC with an approach which electroplates rhodium as the contact plugs in high-aspect ratio devices. Rhodium has lower resistivity than either tungsten or copper, and rhodium plugs can be made thinner as CMOS scaling proceeds.
Before the more radical shifts to air gaps, optical, and carbon nanotubes, these researchers point to improvements in the interconnect stack -- bringing in new metals and kicking out old ones -- at the 32-nm node and beyond.