Linley Newsletter: April 4, 2019

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Linley Newsletter

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Issue #646

April 4, 2019

Independent Analysis of Microprocessors and the Semiconductor Industry

Editor: Tom R. Halfhill

Contributors: Linley Gwennap, Mike Demler, Bob Wheeler

In This Issue:

- MIPS Openly Challenges RISC-V

- ST MCUs Make a Stellar Debut

Linley Spring Processor Conference 2019

FREE Registration Ends Today!

April 10-11, 2019

Hyatt Regency Hotel, Santa Clara, California

Register today for the Linley Spring Processor Conference! FREE registration for qualified attendees ends at 5 p.m. Pacific Time on Thursday, April 4. The on-site registration fee is $195 for qualified attendees or $995 for unqualified attendees.

This two-day event includes technical presentations, new product disclosures, and panel discussions focusing on the processors and IP cores used in deep learning, embedded, communications, IoT, and server designs. An open-bar reception with food and exhibits concludes the first day. We also have two keynotes:

"A Deep Dive Into Deep Learning," by Linley Gwennap, Principal Analyst, The Linley Group

"After Meltdown and Spectre: Security Concerns Facing Contemporary Microarchitectures," by Jon Masters, Computer Architect, Red Hat

This conference is for service providers, equipment vendors, system designers, chip designers, software developers, press, and the financial community. Registration is FREE for those qualified applicants who apply by Thursday, April 4. Click here to view the program or to register:

Sponsors: Arm, Intel, SiFive, Flex Logix, Arteris IP, Cadence, Synopsys, Ceva, Inside Secure, Micron, Andes Technology, Wave Computing, eSilicon, Rambus, and the Embedded Vision Alliance.

MIPS Openly Challenges RISC-V

By Linley Gwennap

In a bold move, MIPS is offering its eponymous instruction-set architecture (ISA) to developers without any license fees or royalties. The strategy, called MIPS Open, is an attempt to boost interest in and usage of the venerable architecture while balancing the company's need to maintain a revenue stream. The MIPS Open community is now on line, and the company has formed a committee to advise on managing the ISA and developing future extensions.

More than 8.5 billion MIPS chips have shipped over three decades, showing that the ISA is production ready and built to handle a variety of applications ranging from microcontrollers and workstations to networking and automotive safety. During this time, the team has developed a broad instruction set with extensions to support this range of systems. MIPS Open comprises Release 6, the most recent version of the full ISA.

The company will also release one of its older CPU cores, microAptiv, with a similar no-fee license. This core is similar to Cortex-M4 in performance and DSP extensions, but Arm users must pay a license fee for the M4 and other recent CPUs. MIPS continues to offer other MIPS cores, including newer M-series models as well as the more powerful I- and P-series, under standard licensing terms and fees.

The open-source RISC-V architecture has built considerable momentum in the past two years, but MIPS Open boasts considerable advantages. For example, RISC-V currently provides few ISA extensions, although additional extensions are in the committee process. To avoid software fragmentation, MIPS Open offers a certification process, which RISC-V lacks. MIPS Open also includes a greater degree of patent protection. These characteristics will particularly appeal to large companies that want to avoid high ISA license fees but are uncomfortable with RISC-V.

Microprocessor Report subscribers can access the full article:

ST MCUs Make a Stellar Debut

By Mike Demler

STMicroelectronics' new Stellar MCUs include a hardware security module (HSM) designed to secure wireless communications and in-vehicle networks. They're the first commercial MCUs with phase-change memory -- a nonvolatile alternative to embedded flash memory that can retain programming up to 165ºC -- allowing them to handle high-temperature automotive operation.

Stellar is ASIL D compliant and guarantees operation over a junction-temperature range of -40°C to +165°C. ST has been developing PCM technology for 15 years, using patents it licensed for work that originated at Stanford in the 1960s. To manufacture Stellar, the company added PCMs to the 28nm FD-SOI process at its Crolles, France, fab.

To meet ASIL D redundancy requirements, the chips have 12 Cortex-R52 CPUs operating as six lockstep pairs. They also integrate three Cortex-M4 CPUs, each with floating-point and DSP extensions. One M4 serves as the HSM's secure core; the other two accelerate data routing and sensor fusion as well other application-specific signal processing. The two M4 application cores and lockstep Cortex-R52 CPUs have access to dedicated portions of the 16MB PCM for nonvolatile program storage, and they use an 8MB SRAM to accelerate real-time response.

Stellar targets next-generation automobiles, which replace multiple ECUs with more-highly integrated domain controllers. Carmakers traditionally distributed ECUs throughout the vehicle, but advanced driver-assistance systems (ADASs) must integrate signals from multiple sensors, using more-powerful multicore processors to handle chassis stability, drivetrain control, and other functions. ST is sampling the first Stellar model to lead customers now. Tier One customers have built ECUs and are performing road tests. The company expects to complete technology qualification in 2020.

Microprocessor Report subscribers can access the full article:

About Linley Newsletter

Linley Newsletter is a free electronic newsletter that reports and analyzes advances in microprocessors, networking chips, and mobile-communications chips. It is published by The Linley Group. To subscribe, please visit:

Domain: Electronics
Category: Semiconductors

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