Linley Newsletter: August 10, 2017

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  10th-Aug-2017
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Linley Newsletter
(Formerly Processor Watch, Linley Wire, and Linley on Mobile)
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Issue #560
August 10, 2017

Independent Analysis of Microprocessors and the Semiconductor Industry

Editor: Tom R. Halfhill
Contributors: Loyd Case, Mike Demler, Linley Gwennap, Bob Wheeler

In This Issue:

- Andes Dual Issues New CPU Cores
- Cavium Scales Down Xpliant Switch
- HiFi 3z Handles Advanced Audio
- Synopsys EV6x Serves Up Big MACs

Did you miss our Linley IoT Hardware Conference?
Free videos are now online!

IoT Technology Trends and Market Forecast
By Mike Demler, Senior Analyst, The Linley Group

This video features our top-down IoT market analysis and five-year forecast, along with a discussion of key technology trends that are driving IoT growth.

Segmenting the IoT Processor Market
By Linley Gwennap, Principal Analyst and President, The Linley Group

This video describes how we segment the IoT processor market in our annual "Guide to Processors for IoT and Wearables." Linley describes wireless processors supporting 802.15.4, Bluetooth, Wi-Fi, and narrow-band LTE, and compares the leading devices in each category.

Both videos are free to view:
http://www.linleygroup.com/events/event.php?num=41

Proceedings are also available for free download. The conference agenda included hardware designs for applications such as smart cities, smart grids, smart farms, smart homes, connected vehicles, and industrial IoT, along with wearables, health, and fitness devices. Proceedings are free with online registration:
http://www.linleygroup.com/events/proceedings.php?num=41

Andes Dual Issues New CPU Cores
By Loyd Case

Andes Technology continues to release CPU intellectual property (IP) at a rapid clip. Its new superscalar AndesCore N15 delivers a twist on dual-issue CPU architecture, and its RISC-V portfolio now includes the 32-bit N25. The N15 RTL is available for licensing, and the N25 RTL is slated to arrive in 3Q17. Andes launched the two new IP cores at the recent Linley IoT Hardware Conference.

The N15 is the company's most powerful CPU core and its first superscalar design. It implements an asymmetric dual-issue pipeline with six stages, and it offers a DSP option. The design includes dynamic branch prediction and an optional memory-management unit (MMU), enabling it to boot a full Linux operating system. The company positions the N15 as the successor to the N10, a single-issue CPU with a five-stage pipeline and optional DSP. It aims the N10 at more-sophisticated IoT applications that require signal-processing and floating-point support, such as voice-enabled speakers. The N15 delivers higher performance than the older N10 at the expense of greater power.

Yet the N15 may be the final hurrah for the AndeStar V3 instruction-set architecture (ISA), as the company is looking to RISC-V for future cores. The N25 closely resembles the NX25, replacing the 64-bit elements of the latter CPU with a RISC-V RV32IMAC-compliant 32-bit microcore. In addition to the basic RISC-V ISA, the Andes cores implement proprietary extensions to improve performance and simplify the transition from the company's original ISA. Thus, code compiled for RV32 will run on the N25, but code that takes full advantage of the Andes design won't run on generic RISC-V cores. The company calls this extended RISC-V version its AndeStar v5 ISA. The new core implements AndeStar V5m, a 32-bit version more suitable for MCUs.

Microprocessor Report subscribers can access the full article:
http://www.linleygroup.com/mpr/article.php?id=11843

Cavium Scales Down Xpliant Switch
By Bob Wheeler

While other switch-chip vendors have introduced products for 200G and 400G Ethernet, Cavium has instead moved down market. Its new XP60 and XP70 switch chips represent the second-generation Xpliant design, named after the startup Cavium acquired in 2014. They target 10G Ethernet and 25G Ethernet, respectively, and range from 1.8Tbps down to 280Gbps in aggregate bandwidth. The new chips expand Cavium's addressable markets to include enterprise and carrier-access networks as well as mainstream cloud data centers.

The company sampled the new XP60 and XP70 families in 2Q17. The top XP70 variant (CNX78072) offers 72x25Gbps serdes for 1.8Tbps of aggregate bandwidth. It handles up to 18x100GbE ports, 72x25GbE ports, or a mix of the two speeds. A 48x25GbE + 6x100GbE top-of-rack (ToR) switch is a typical configuration.

Another version, the CNX78061, provides 48x10GbE + 6x100GbE ports. The XP60 models offer only 10GbE/40GbE ports, and the top-end CNX68028 has 72x10Gbps serdes for 720Gbps total. The XP60 and XP70 are more than just derivatives of Cavium's first-generation chip; they include significant architectural enhancements to improve delivered performance and add telemetry features.

By providing customer programmability, the XP60 and XP70 should appeal to customers that wish to implement custom features. Although Cavium must face Broadcom as it enters new Ethernet switching segments, it's avoiding the increasingly crowded hyperscale-data-center market. Given its success in the embedded market, we think extending Xpliant outside of data centers is an effective growth strategy.

Microprocessor Report subscribers can access the full article:
http://www.linleygroup.com/mpr/article.php?id=11840

HiFi 3z Handles Advanced Audio
By Linley Gwennap

Cadence announced its newest audio DSP, called HiFi 3z, at the recent Linley IoT Hardware Conference. This new intellectual-property (IP) core can perform eight 16x16-bit MACs per cycle, doubling the compute capability of its predecessor, HiFi 3. It increases the 16-bit MAC performance rather than 24 or 32 bit, making it particularly useful for EVS and other 16-bit codecs.

To feed more data into the compute units, particularly for EVS and other data-intensive codecs, the company added a second 64-bit path from the local data memory into the core. The three-way VLIW architecture now supports a load operation in the second slot in addition to the load/store unit in the first slot.

Whereas object-based audio codecs don't benefit from 16-bit MACs, they require more control code to properly place each sound in 3D space. To better handle these and similar algorithms, HiFi 3z adds a scalar unit to the second slot. Thus, scalar-heavy portions of the code can now execute two operations per cycle, whereas the inner loops can shift to more vector (SIMD) operations.

The new design is well suited to the latest audio codecs such as EVS for cellular voice, Dolby AC-4 and MPEG-H for home entertainment, and voice processing in smart speakers. Cadence measured performance improvements of 1.3x for EVS and 1.4x for both Dolby AC-4 and MPEG-H. These gains come with only a minor die-area increase over HiFi 3. Production RTL is now available for licensing, and the first chips using the new IP should enter production around mid-2018.

Microprocessor Report subscribers can access the full article:
http://www.linleygroup.com/mpr/article.php?id=11841

Synopsys EV6x Serves Up Big MACs
By Mike Demler

Synopsys has upgraded its DesignWare EV6x family of embedded-vision processor cores, adding new configurations that enable designers to include up to four convolutional-neural-network (CNN) accelerators. Together, these accelerators comprise a massive 3,520 single-cycle multiply-accumulators (MACs).

When manufactured in a 16nm FinFET process, the new EV6x can clock at up to 1.28GHz, delivering peak CNN performance of 4,500 GMAC operations per second (GMAC/s). The company plans to release the latest EV6x intellectual property (IP) for general licensing by the end of August.

Whereas the EV6x models that Synopsys unveiled last year optionally include a single 880-MAC accelerator, the upgrades allow designers to integrate one, two, or four of the convolution and classification engines. The maximum configuration offers CNN acceleration similar to that of the dual 2,048-MAC deep-learning accelerators in Nvidia's new Xavier SoC. That product delivers 5,120GMAC/s to power Level 4/5 autonomous-driving systems.

As in the initial design, the new EV6x uses 12-bit integer MACs to offer a middle ground between the typical 8- and 16-bit units in other computer-vision (CV) cores. The 12-bit MACs consume only half the silicon area of 16-bit MACs, and they yield higher accuracy than 8-bit integer CV cores.

The scalability of the EV6x in CPUs/DSPs and CNN accelerators enables licensees to tune it for a wide range of embedded-vision tasks. Although designers who can accept the lower precision of an 8-bit CNN may prefer a core built for that resolution, the upgraded EV6x architecture offers performance that matches the best licensable CV IP.

Microprocessor Report subscribers can access the full article:
http://www.linleygroup.com/mpr/article.php?id=11842

About Linley Newsletter

Linley Newsletter is a free electronic newsletter that reports and analyzes advances in microprocessors, networking chips, and mobile-communications chips. It is published by The Linley Group and consolidates our previous electronic newsletters: Processor Watch, Linley Wire, and Linley on Mobile. To subscribe, please visit:
http://www.linleygroup.com/newsletters/newsletter_subscribe.php

Domain: Electronics
Category: Semiconductors
SEMICONDUCTOR ANALYTICS

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