Linley Newsletter: February 7, 2019

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Issue #638

February 7, 2019

Independent Analysis of Microprocessors and the Semiconductor Industry

Editor: Tom R. Halfhill

Contributors: Linley Gwennap, Mike Demler, Bob Wheeler, David Kanter

In This Issue:

- Intel's Sunny Cove Sits on an Icy Lake

- WD Rolls Its Own RISC-V Core

- Ceva's BX Hybrid Boosts DSP Engine

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Intel's Sunny Cove Sits on an Icy Lake

By David Kanter

The heart of Intel's forthcoming 10nm Ice Lake family, the Sunny Cove CPU, boasts nine specialized ISA extensions and greater per-core performance with up to 33% more cache bandwidth. The 10nm technology will also reduce power for the new microarchitecture.

The new ISA extensions round out AVX-512 by promoting various instructions and by adding several security-focused instructions. In addition, the company expanded the virtual and physical address space and enabled comprehensive memory encryption, a huge boon for server processors. The extra transistor budget from the 10nm process allows the CPU to implement a larger out-of-order window, additional integer and vector execution units, and a second store pipeline.

The multiyear 10nm delays mean Sunny Cove will be Intel's first new big core with out-of-order capability in four years. The company has maintained its leadership without major microarchitecture changes largely thanks to heroic optimization of the 14nm node. But transistor optimizations in an existing process can only achieve so much. The perceived lack of innovation may be a problem for the PC market, even as Intel's first major competition arrives in 2019 when AMD begins shipping CPUs on 7nm TSMC technology.

Against that backdrop, Sunny Cove can't come soon enough. It will enable new processors that can reinvigorate PCs and satisfy demanding data-center customers, but Intel's product groups and manufacturing must deliver on these promises. Although the first Sunny Cove-based chips are slated for production in 4Q19, rolling the new CPU into all of the company's numerous products will last well into 2020.

Microprocessor Report subscribers can access the full article:

WD Rolls Its Own RISC-V Core

By Bob Wheeler

Storage vendor Western Digital (WD) has declared independence from licensed CPUs by designing its own RISC-V core. SSD controllers are the first application for its new Swerv EH1 RISC-V CPU. Flash-based products now represent about half its revenue, and WD designs both 3D NAND chips and associated controllers. Over the next several years, it plans to move most of its controller shipments -- representing more than one billion CPUs -- from licensed to in-house designs. The company has also made the Swerv design available as open source.

Owing to its target application, WD designed the Swerv EH1 as a simple 32-bit real-time core that offers relatively high performance. It implements only the RV32I base ISA plus the multiply and divide (M) and compressed (C) extensions. Its dual-issue in-order pipeline delivers a competitive 5.0 CoreMarks per megahertz. WD completes the core with an instruction cache, tightly coupled memories (TCMs) for instructions and data, an interrupt controller, a debug block, and four 64-bit AXI buses for memory and I/O. Although it aimed for 1.0GHz worst-case operation in TSMC 28nm technology, it achieved 1.8GHz operation in a typical process corner.

The Swerv EH1 is similar to SiFive's new E76 CPU, which achieves slightly lower clock speeds and CoreMarks per megahertz. Last April, WD announced an investment and multiyear license agreement with SiFive, but Swerv is separate from that agreement. Instead, the two companies independently developed dual-issue RISC-V CPUs. Owning Swerv gives WD maximum control over deeply embedded designs. At the same time, it can use third-party RISC-V CPUs or processors (chips) for higher-end products such as storage systems.

Microprocessor Report subscribers can access the full article:

Ceva's BX Hybrid Boosts DSP Engine

By Mike Demler

Ceva's new BX DSP cores offer upgrades to the first-generation X-series models, which employ a hybrid architecture combining multicore scalar CPUs for control functions with a highly configurable five-way SIMD/VLIW DSP engine for signal processing. The new intellectual property (IP) core tightens security by using a TrustZone-like memory subsystem to isolate secure applications from nonsecure ones.

Architectural enhancements double the fixed-point DSP performance compared with the previous generation, and floating-point DSP operations receive up to an 8x boost. The single-core BX1 targets NB-IoT basebands and sensor fusion, and the dual-core BX2 targets 5G PHY control, multi-microphone beam forming, and speech-recognition neural networks. Both models are available now to lead customers, and the company plans to release them for general licensing by the end of 1Q19.

The single-CPU BX1 and dual-CPU BX2 are similar to the previous X1 and X2, respectively, but they increase the maximum pipeline depth from 10 stages to 11. For designs manufactured in 7nm technology, Ceva expects the cores to run at up to a 2.0GHz clock frequency. CPU performance rises slightly from 4.3 CoreMarks per megahertz in the X2 to 4.5 in the BX2.

The multipurpose BX IP cores will compete against Arm's Cortex-M4 and Cortex-M7 CPUs with DSP extensions, as well as the latest Cortex-M33. They improve on the first-generation X-series, but they're also likely to attract Cortex-M customers that need better DSP performance.

Microprocessor Report subscribers can access the full article:

About Linley Newsletter

Linley Newsletter is a free electronic newsletter that reports and analyzes advances in microprocessors, networking chips, and mobile-communications chips. It is published by The Linley Group. To subscribe, please visit:

Domain: Electronics
Category: Semiconductors

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