Linley Newsletter: July 19, 2018

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Linley Newsletter

(Formerly Processor Watch, Linley Wire, and Linley on Mobile)

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Issue #609

July 19, 2018

Independent Analysis of Microprocessors and the Semiconductor Industry

Editor: Tom R. Halfhill

Contributors: Linley Gwennap, Mike Demler, Bob Wheeler

In This Issue:

- Adreno 630: Small But Mighty

- NXP S23S Drives Autos in Lockstep

- eSilicon 7nm Serdes Hits 56Gbps

Coming Soon: Communications Semiconductor Market Forecast 2017-2022

The Linley Group is pleased to announce the upcoming release of the 12th edition of our "Communications Semiconductor Market Forecast."

This report provides the detailed information needed to understand the complexities of the communications semiconductor market. Chip vendors, investors, and OEMs can readily see how large are the mature product markets and how fast the emerging categories are growing. New in this edition is a forecast for 400G Ethernet switch and PHY chips.

A detailed description of the report, including the table of contents, is available on our web site:

Special offer: Get a pre-publication discount of $500 off the corporate license or $300 off a single license until August 13, 2018. For more information or to order the report, please email us at


Adreno 630: Small But Mighty

By Linley Gwennap

Our comparison of premium mobile graphics units shows Qualcomm leading in both performance and die area, yielding stellar efficiency for its Adreno 630. This GPU, which appears in the Snapdragon 845, has only four shader cores but relies on hard-wired acceleration logic to boost its performance. This logic is more compact than programmable cores, increasing both performance per watt and per square millimeter of die area.

By contrast, Samsung implemented 18 Mali-G72 shader cores in its Exynos 9810. The Arm GPU design relies heavily on these cores for most graphics tasks and has relatively little common logic. The GPU requires twice the die area of the Adreno 630 while delivering less performance on the GFXBench tests. Both processors were tested in Galaxy S9+ smartphones with equivalent power and thermal capabilities.

Apple says it designed the GPU in its A11 processor (which appears in the iPhone 8 and iPhone X), but that GPU retains certain features from the A10, which used a PowerVR GPU licensed from Imagination Technologies. Although Apple says the A11 has three cores, our analysis of the die photo identifies six shader cores in three pairs, with each pair sharing a texture unit. The A10 similarly features six cores, and the shared texture unit is a hallmark of the PowerVR design.

Although Intel no longer competes in smartphones, we also analyzed the GPU from the Core M3-7Y30, a Kaby Lake design that appears in the Microsoft Surface Pro and other Windows tablet PCs. The Intel chip's HD Graphics 615 GPU delivers the lowest performance in this group, yet it has a larger die than even the massive 18-core Mali. When adjusted for Intel's lagging IC process, the two GPUs are about the same size, but HD Graphics still trails in performance per watt.

Microprocessor Report subscribers can access the full article:

NXP S32S Drives Autos in Lockstep

By Tom R. Halfhill

Failure is not an option when a motor vehicle must stop. To ensure that a human driver or autonomous system always maintains control, the vehicle's processors must respond under any conditions, including faults that would cripple a conventional chip. So NXP has announced a fault-tolerant automotive processor that runs four pairs of CPUs in lockstep mode. It designed the S32S247 for "any system that starts, stops, or steers the vehicle."

As the first member of the S32S family, the new chip is also the first announced product to use Cortex-R52, a synthesizable CPU that Arm designed specifically for critical control. This 32-bit core supersedes the eight-year-old Cortex-R5 and is the first implementation of the Arm v8-R instruction-set architecture (ISA) announced in 2013. To host hypervisors, the R52 adds another privilege level and a second memory-protection unit (MPU). To isolate critical tasks, it can simultaneously run multiple real-time operating systems in virtual sandboxes, and it speeds up context switching and interrupt handling.

Scheduled to sample in 4Q18 and start production in 2020, the octa-core S32S247 appears to the system as a quad-core processor. It arranges its eight CPUs in pairs. Each CPU can run its own RTOS and copy of the same control software in a sandboxed partition. The first pair is the "safety core," which handles errors in addition to its usual functions. Each CPU pair continuously operates in lockstep mode, with the "shadow" core following two clock cycles behind the main core. A redundancy control and checker unit (RCCU) compares their outputs. If the RCCU detects a discrepancy, it notifies the safety core, which takes corrective action.

By announcing the chip now, NXP hopes to lock in some long-term customers and shut the opportunity window on rivals. The S32S247 surely isn't the only Cortex-R52 automotive chip in the works, but it wins the pole position.

Microprocessor Report subscribers can access the full article:

eSilicon 7nm Serdes Hits 56Gbps

By Mike Demler

ASIC provider eSilicon specializes in high-performance devices for communications infrastructure, networking, and other data-center applications. Using 7nm TSMC technology, it has developed ASIC-design platforms under the NeuASIC brand. Each includes hard and soft macros for networking applications along with a new architecture and intellectual-property (IP) library for building AI accelerators.

The NeuASIC platforms give designers a variety of power-optimized memory compilers, serdes, and 2.5D-IC interposers. The 7nm library includes a 56Gbps serdes, High Bandwidth Memory 2 (HBM2) PHY, and ternary-content-addressable-memory (TCAM) compiler, as well as networking-optimized I/Os and other components.

In 2017, after Marvell shut down most of its European operations, eSilicon acquired the Italian engineering team that had developed a 56Gbps Marvell serdes for manufacture in 28nm technology. That group used the same ADC/DSP-based architecture to develop a 7nm serdes, which now appears in the NeuASIC platforms and is available separately as a licensable core. This new serdes enables PAM4 and NRZ coding, and its programmability allows designers to tune power/performance for long or short channels.

To maximize memory bandwidth, the company manufactures networking products in 2.5D packages using silicon interposers to combine the ASIC die with stacked DRAM chips. For AI accelerators, NeuASIC will enable designers to integrate a custom deep-learning accelerator (DLA) in an ASIC chassis comprising a CPU, scratchpad RAM, and HBM2 interfaces.

Microprocessor Report subscribers can access the full article:

About Linley Newsletter

Linley Newsletter is a free electronic newsletter that reports and analyzes advances in microprocessors, networking chips, and mobile-communications chips. It is published by The Linley Group and consolidates our previous electronic newsletters: Processor Watch, Linley Wire, and Linley on Mobile. To subscribe, please visit:

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Domain: Electronics
Category: Semiconductors
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