Linley Newsletter: July 20, 2017

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Linley Newsletter

(Formerly Processor Watch, Linley Wire, and Linley on Mobile)
Please feel free to forward this to your colleagues

Issue #557
July 20, 2017

Independent Analysis of Microprocessors and the Semiconductor Industry

Editor: Tom R. Halfhill
Contributors: Linley Gwennap, David Kanter, Loring Wirbel

In This Issue:

- Skylake-SP Scales Server Systems
- Xeon Scalable Reshapes Server Line
- Snapdragon 450 Moves to 14nm
- Achronix Turns to Embedded FPGAs

Coming Soon:
"A Guide to Ethernet Switch and PHY Chips" (13th Edition)

We are wrapping up our new report "A Guide to Ethernet Switch and PHY Chips" (13th Edition) by principal analyst Bob Wheeler and senior analyst Loring Wirbel.

This report provides extensive coverage of Ethernet switch chips for data centers, including those for 10G, 25G, 50G, 100G, and 400G Ethernet. It also includes physical-layer (PHY) chips for 10GBase-T and 100G Ethernet. Vendors covered include Barefoot Networks, Broadcom, Cavium, Centec, Innovium, Intel, Marvell, Mellanox, and Nephos (Mediatek), as well as PHY vendors Aquantia and Inphi.

New coverage in this edition:

- Broadcom's Tomahawk II, Trident 3, and Jericho+ Ethernet switch chips;

- Marvell's Bobcat 3 25G Ethernet switch;

- Barefoot Networks' Tofino programmable switch;

- Innovium's 12.8Tbps Teralynx switch;

- Cavium's Xpliant programmable switch;

- Updated 2016 market size and vendor shares for GbE switch chips, 10GbE switch chips, and 10GbE PHYs;

- Updated market forecasts for GbE through 100GbE switch chips as well as 10GbE and 100GbE PHYs, 2016-2021.

Special Offers!

We can offer you a pre-publication discount of $500 off the regular corporate license of $5,995, or $300 off the regular single-copy license of $4,495. Offers expire on July 28, 2017.

The preliminary table of contents and additional information can be found on our web site: http://www.linleygroup.com/ethernet-switch

For more information or to order the report, please email us at cs@linleygroup.com.

Skylake-SP Scales Server Systems
By David Kanter

Over the last 25 years, Intel has gradually shifted from reusing client processors in the data center to designing server-centric platforms. The new Purley platform and 14nm+ Skylake-SP processor are the final stage of this evolution, as they fully differentiate server processors from client processors. Instead of simply reusing the client CPU and extending the client ring fabric to greater core counts, Intel extensively modified the CPU to boost performance on server workloads.

The Skylake-SP CPU core clearly descends from the Skylake client core, but it boasts a larger 1MB L2 cache and AVX-512 support, including 512-bit-wide vector units. The new on-die mesh fabric no longer resembles the lower-bandwidth client ring fabric, and the L3 cache is noninclusive with smaller 1.375MB slices. Similarly, the memory and I/O controllers provide greater performance and connectivity. Skylake-SP also has the new Ultra Path Interconnect (UPI), a coherent system interface that's faster and more efficient than the client's Quick Path Interconnect (QPI). The server processor targets 70-205W TDPs, barely overlapping those of PC processors.

Living up to its name, Intel is integrating more pieces of the system architecture. Like Xeon Phi, Skylake-SP offers in-package Omni-Path adapters for high-performance computing (HPC). In addition, the Lewisburg south-bridge chip (platform-controller hub, or PCH) has 10G Ethernet (10GbE) and Non-Volatile Memory Express (NVMe) controllers. At the same time, Skylake-SP will bring heterogeneous computing to mainstream servers. Intel can integrate accelerators such as FPGAs and Nervana neural-network accelerators in the processor package, and the south bridge comes with dedicated cryptography and compression hardware.

Skylake-SP is designed for a range of server tasks, including cloud services, enterprise applications, HPC, storage, and networking. It covers a wide range in performance, power, and price. Furthermore, the new platform delivers a substantial performance boost without requiring a process shrink to increase transistor density.

Microprocessor Report subscribers can access the full article:
http://www.linleygroup.com/mpr/article.php?id=11834

Xeon Scalable Reshapes Server Line
By David Kanter

The new Xeon Scalable processors (formerly Skylake-SP) cover a lot of ground, from low-end servers to high-performance-computing (HPC) designs. To capture the breadth of new offerings, Intel has rolled out a new branding scheme that replaces the Xeon E5 and E7 with five families of increasing capabilities and prices, ranging from $200 "Bronze" processors to $13,000 "Platinum" processors. For the premium models, the new Xeon promises 35-70% greater performance on certain workloads.

Naturally, Intel hopes this new lineup will entice customers to buy more-expensive products. It's reserving for the top tiers many of the most interesting new features, such as additional AVX-512 execution units and integrated Omni-Path fabric. This restriction, however, will unfortunately limit adoption of some of these features, especially AVX-512. Intel is also taking the opportunity to charge a price premium for models with high memory capacity.

Skylake-SP, part of the new Purley platform, is a significant upgrade to last year's Broadwell-EP/Grantley platform (Xeon E5v4), delivering more per-core performance, more cores, more memory channels, and more PCIe lanes. Compared with the Broadwell-EX/Brickland platform (Xeon E7v4), the elimination of external memory buffers eases board design and reduces power, but it reduces the memory capacity as well. The new processors also enable an in-package 100Gbps Omni-Path fabric and accelerators such as FPGAs. The south bridge now offers up to four 10G Ethernet ports with iWARP RDMA.

Despite some minor shortcomings, the Xeon Scalable processors are technically impressive and show considerable benefits, especially in the premium 6100- and 8100-series. Historically, Intel has been generous with the bounty of Moore's Law and always seemed to split performance gains with customers while gradually increasing prices. The new products generally follow this trend. Thus, the new processors are solid and long-awaited upgrades for most customers.

Microprocessor Report subscribers can access the full article:
http://www.linleygroup.com/mpr/article.php?id=11833

Snapdragon 450 Moves to 14nm
By Linley Gwennap

Qualcomm has brought a 14nm processor into its low-cost line for the first time, boosting performance and power efficiency. The new Snapdragon 450 upgrades the Snapdragon 435, offering 25% faster CPUs, twice the video speed, greater camera resolution, and other improvements. In addition to increasing performance, the shrink from 28nm to 14nm reduces power consumption for a fixed set of tasks, extending battery life by up to four hours, according to Qualcomm. The 450 is due to appear in smartphones by the end of this year; it targets devices costing as little as $150.

The 450 includes Qualcomm's Adreno 506 GPU, which scores 10fps on the Manhattan 1080p benchmark -- 30% better than the Snapdragon 435. The company expects graphics performance to rise 25% across a range of benchmarks. As with the CPUs, the GPU will use about 30% less power on the same tasks, extending battery life when running a particular mobile game, for example.

Whereas the 435 supports dual 8MP cameras, the 450 can handle dual 13MP cameras. The new processor also improves the image signal processor (ISP); for example, it can now provide real-time bokeh. Although other Snapdragon 400 processors can apply this effect to blur the background in an image, the 450 can apply it to the live image on the display, providing a better preview of the photo.

The new processor supports 1080p (FHD) video encoding and decoding at 60fps, twice the 435's frame rate. This higher rate enables smoother video capture and playback, particularly for fast-moving scenes. The video resolution is appropriate for the maximum display size of FHD+, which represents a standard FHD display extended to 18:9 resolution for taller phones.

Microprocessor Report subscribers can access the full article:
http://www.linleygroup.com/mpr/article.php?id=11831

Achronix Turns to Embedded FPGAs
By Loring Wirbel

Achronix launched its first Speedcore embedded-FPGA intellectual property (IP) in 2016 and anticipates launching Speedchip FPGA "chiplets" for 2.5D packages next year. This strategy places the company's high-performance Speedster FPGAs in a supporting role. It also reflects more than just changing customer needs: Achronix recognizes that direct competition with Xilinx and Intel could prove impossible. Although Intel is the foundry for the newest Speedster line, it has been an Achronix competitor since its 2015 purchase of Altera.

The Speedcore embedded FPGA (eFPGA) offers three types of expandable IP blocks along with customer-defined mixes of reconfigurable logic blocks (RLBs), block-RAM elements, and 64-bit DSPs. An RLB includes four quad-input lookup tables (LUTs), flip-flops, and a 4-bit ALU. Each DSP block has an 18x27-bit multiplier, a 64-bit accumulator, and a 27-bit pre-adder. Achronix refrains from defining I/O blocks, as it intends the IP to be wholly embedded in a customer's ASIC. It offers the Achronix CAD Environment (Ace) design tools, which integrate with standard electronic-design-automation (EDA) environments. But like an ASIC vendor, it provides back-end verification services.

The company's most immediate competition could come from Flex Logix and other embedded-IP specialists, but its challenge is in effectively moving away from catalog FPGA devices. The company says its annual revenue will exceed $100 million for the first time in 2017, and design starts for the new Speedcore are showing considerable growth. These designs initially employed 50k to 150k LUTs, but some recent ones have 10k to 20k. Although the first customers were OEMs, Achronix is seeing interest from chip companies wishing to embed Speedcore in their ASSPs.

Microprocessor Report subscribers can access the full article:
http://www.linleygroup.com/mpr/article.php?id=11832

About Linley Newsletter

Linley Newsletter is a free electronic newsletter that reports and analyzes advances in microprocessors, networking chips, and mobile-communications chips. It is published by The Linley Group and consolidates our previous electronic newsletters: Processor Watch, Linley Wire, and Linley on Mobile. To subscribe, please visit:
http://www.linleygroup.com/newsletters/newsletter_subscribe.php

Our previous subscription newsletters -- Microprocessor Report, Networking Report, and Mobile Chip Report -- are now consolidated in a single subscription newsletter: Microprocessor Report. MPR publishes articles with significantly more detail on the subjects covered in our free electronic newsletter. To subscribe, please visit:
https://www.linleygroup.com/mpr/subscribe.php
...or contact us at 408.270.3772; cs@linleygroup.com.

Domain: Electronics
Category: Semiconductors

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