Linley Newsletter: March 15, 2018

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Linley Newsletter

(Formerly Processor Watch, Linley Wire, and Linley on Mobile)

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Issue #591

March 15, 2018

Independent Analysis of Microprocessors and the Semiconductor Industry

Editor: Tom R. Halfhill

Contributors: Linley Gwennap, Mike Demler, Bob Wheeler

In This Issue:

- Xeon D Soars With Skylake

- Ceva PentaG Adds AI to 5G Baseband

- Helio P60 Targets "New Premium"

- Broadcom Router Chips Aim at ASICs

Agenda for Linley Spring Processor Conference 2018

The Linley Group has announced the agenda for the Linley Spring Processor Conference on April 11-12 at the Hyatt Regency in Santa Clara, California. At this single-track event, speakers will describe new chips, IP cores, and processor technologies to address deep learning, embedded, communications, automotive, IoT, and server designs.

On April 11, principal analyst Linley Gwennap will deliver the first keynote address: how AI is affecting processor design in applications ranging from data centers to IoT. On April 12, Western Digital CTO Martin Fink will deliver another keynote: how big-data and edge-processing trends drove his company to select RISC-V.

The rest of the two-day program features 20 curated technical presentations that cover processor technologies and applications, including data-center technologies, SoC IP and design tools, autonomous vehicles, IoT security, CPU and connectivity IP, and AI in IoT and edge devices. Attendees can interact with speakers and other industry leaders, network with other designers, and attend an evening reception on April 11 with sponsor exhibits and demos.

For a complete schedule, visit our web site:

Admission is FREE to qualified attendees who register online by April 5, 2018. This conference is for service providers, equipment vendors, system designers, chip designers, software developers, press, and the financial community. Free admission sponsored by Synopsys, Arm, Micron, Rambus, GlobalFoundries, NetSpeed Systems, ArterisIP, Cadence, CEVA, InsideSecure, SiFive, UltraSoc, Videantis, Wave Computers, and the MIPI Alliance.

Xeon D Soars With Skylake

By Tom R. Halfhill

Intel's Xeon D family is leaping to Skylake. The new Xeon D-2100 products now have Skylake-SP CPUs and raise the maximum core count from 16 to 18. Compared with most of the older Broadwell-based Xeon D processors, they also double the DRAM bandwidth, quadruple the DRAM capacity, double the number of 10 Gigabit Ethernet ports, and offer more PCI Express lanes and Serial ATA interfaces. Some models have QuickAssist cryptography acceleration, and all are shipping now for servers and embedded systems.

In most respects, the D-2100 family is a major advance over the D-1500 Broadwell processors that shipped in 2015-2016. Intel foreshadowed the new products last year by quietly introducing the Xeon D Network Series -- five Broadwell models that also have four 10GbE ports and QuickAssist acceleration. Like those chips, the new family pushes the maximum base clock frequency a smidgen higher (2.3GHz versus 2.2GHz). But the Broadwell Network Series peaks at eight cores. The D-2100 line uses the enhanced 14nm+ FinFET process to integrate up to 18 cores and employs the same Skylake-SP microarchitecture as the higher-end Xeon Scalable family.

Essentially, the new processors copackage a Xeon Scalable die with a C600-series south-bridge die (code-named Lewisburg). To avoid cannibalizing Xeon Scalable sales, they omit some features. Even so, they're powerful processors that serve a broader application spectrum than previous Xeon D products. But they use more power and cost more than similar chips from AMD and Broadcom.

Microprocessor Report subscribers can access the full article:

Ceva PentaG Adds AI to 5G Baseband

By Mike Demler

Ceva's new PentaG DSP comprises a set of configurable processing blocks that allow designers to build digital basebands implementing the recently ratified 3GPP 5G New Radio (5G-NR) specification. This intellectual property (IP) includes the company's previously released XC-4500 LTE-Advanced DSP and X2 PHY controllers, enabling backward compatibility with previous-generation cellular standards. But it also extends the XC-4500 ISA with 5G-specific instructions and adds hardware accelerators for the new 5G channel-coding formats.

Other new PentaG features include a vector multiply-accumulate (MAC) coprocessor and a neural-network engine that delivers 400 billion operations per second (GOPS). The neural engine runs deep-learning algorithms that handle 5G link optimization.

PentaG targets enhanced-mobile-broadband (EMBB) services using 5G-NR, which network operators plan to roll out in 2019. The initial non-standalone (NSA) mode uses existing LTE infrastructure for core network functions, but it can theoretically deliver up to 10Gbps peak downlink speeds, rolling off to 100Mbps at cell edges. Ceva's new baseband intellectual property (IP) is suitable for gigabit 5G radios in smartphones as well as for embedded devices and fixed-wireless modems. It supports the initial 5G-NR deployments using sub-6GHz and millimeter-wave spectrum, but it's software upgradable to support future 3GPP releases.

PentaG uses a modular approach, allowing customers to choose the components they need to add 5G capabilities to existing designs. The company licenses it as a complete hardware/software platform; alternatively, customers can license each component separately. Ceva plans to begin licensing PentaG to select customers in 2Q18 and to begin general licensing in 3Q18.

Microprocessor Report subscribers can access the full article:

Helio P60 Targets "New Premium"

By Linley Gwennap

As smartphone technology stagnates, the difference between premium and midrange phones becomes harder to detect. MediaTek's new Helio P60 processor blurs that line further, bringing premium features such as "big" CPUs and AI acceleration to a lower price tier. This approach taps into a growing trend among Chinese OEMs such as Lenovo, Oppo, and Vivo: packing high-end capabilities into phones that sell for $200-$400. The P60 will appear in these devices within the next few months.

MediaTek had earlier indicated that as part of a "pause" in its premium-tier line, it didn't plan to update its Helio X30. Yet the new P60 is in some ways more powerful than the X30, allowing lower-price phones to implement many of its high-end features. For example, the P60 features four Cortex-A73 CPUs operating at up to 2.0GHz; the X30 has only two such CPUs, albeit at a faster 2.5GHz. Previous P-series chips employed only "little" Cortex-A53s.

The P60 is also the first P-series processor to feature neural-network acceleration, indicating a growing demand for AI acceleration across all prices. It implements a dual-core AI engine, based on the Cadence Vision P6 intellectual property (IP), that quadruples the peak performance of the premium X30 design.

Validating the emergence of the new mid-premium segment, Qualcomm disclosed plans to release a new family of processors dubbed the Series 700. These products will extend the performance of the mid-tier Series 600 (e.g., Snapdragon 660) while sitting below the premium Series 800 (e.g., Snapdragon 845). The first Series 700 models will sample in the second quarter and should appear in phones before the end of this year, well after the Helio P60 reaches the market.

Microprocessor Report subscribers can access the full article:

Broadcom Router Chips Aim at ASICs

By Bob Wheeler

Service-provider routers continue to rely heavily on OEM-proprietary ASICs. Broadcom, however, has enabled increasingly sophisticated routers based on merchant silicon. Now, its next-generation StrataDNX products are leapfrogging OEM ASICs in port density while also supporting 400G Ethernet. The new chipset comprises Jericho2 for line cards and Ramon for the switch fabric, upgrading network ports and the backplane with 50Gbps PAM4 serdes. A single Jericho2 handles 12x400GbE ports (4.8Tbps), whereas each Ramon delivers 9.6Tbps of fabric bandwidth. Together, they enable a 16-slot chassis switch/router with 230Tbps of front-panel bandwidth.

Sampling now, the new chipset represents the 16nm StrataDNX generation, replacing the 28nm generation first introduced three years ago. Broadcom gave its 28nm line-card device a "midlife kicker" in 2016, with Jericho+ upgrading to 9x100GbE ports. Compared with Jericho+, Jericho2 increases throughput by more than 5x. To achieve this feat without abandoning deep buffers, the company adopted in-package High Bandwidth Memory 2 (HBM2), replacing external GDDR5 SDRAM.

Jericho2 increases packet-processing flexibility through an architectural addition that Broadcom calls Elastic Pipe. It has a pool of programmable elements that can be inserted into any stage of the processing pipeline, enabling feature additions that exceed the standard pipeline's resources. Conceptually, Elastic Pipe is akin to inserting an FPGA into the pipeline to add new capabilities.

For modular systems, Jericho2 and Ramon compete primarily with OEMs' internal ASICs, which typically include a programmable network processor (NPU) and fabric chips. The fastest of these devices now shipping is Nokia's FP4 chipset, which delivers one-quarter the bandwidth of Jericho2. Standard Ethernet switch chips offer a merchant alternative, but they lack the deep buffering of the new design. Having a unique merchant product, Broadcom's strategy is to displace custom ASICs either by convincing OEMs to make the change or by enabling service providers to instead purchase white-box platforms.

Microprocessor Report subscribers can access the full article:

About Linley Newsletter

Linley Newsletter is a free electronic newsletter that reports and analyzes advances in microprocessors, networking chips, and mobile-communications chips. It is published by The Linley Group and consolidates our previous electronic newsletters: Processor Watch, Linley Wire, and Linley on Mobile. To subscribe, please visit:

Domain: Electronics
Category: Semiconductors

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