Linley Newsletter: March16, 2017

 weSRCH's Best of the Internet Award
  17th-Mar-2017
 783

Issue #539
March 16, 2017

Independent Analysis of Microprocessors and the Semiconductor Industry

Editor: Tom R. Halfhill
Contributors: Mike Demler, Loring Wirbel

In This Issue:

- Altair LTE Chip Integrates M1, NB1
- Arteris Piano Tunes Timing
- Helio X30 Nabs Speed Lead
- Smaller Offspring for TI's Sitara

Coming Soon:

"A Guide to Embedded Processors" (10th Edition)

The Linley Group is wrapping up the 10th Edition of "A Guide to Embedded Processors" by senior analysts Jag Bolaria and Tom R. Halfhill. This report provides extensive coverage of 32- and 64-bit high-speed embedded processors with one to four CPU cores. Vendors include AMD, Broadcom (Avago), Cavium, Intel (including Altera and Axxia), Macom (AppliedMicro), Marvell, NXP, Qualcomm, Texas Instruments, and Xilinx.

What's New in This Edition

- NXP's new QorIQ LS1-series processors with ARM CPU cores and the first LA-series ARM-based processor.

- Intel's Goldmont-based Atom processors (Apollo Lake) and Kaby Lake Xeon and Core processors, plus the newest SoC FPGAs acquired with Altera.

- Cavium's new ARMv8-compatible Octeon TX processors.

- Texas Instruments' new ARM-based Sitara processors with integrated DSPs and GPUs.

- Xilinx's new Zynq UltraScale+ MPSoCs with embedded ARM Cortex-A53 cores manufactured in 16nm FinFET technology.

- Broadcom's first 64-bit StrataGX processors with Cortex-A57 cores and the 64-bit BCM4908 with Cortex-A53.

- Marvell's new 64-bit Armada processors using its modular chip (MoChi) architecture, plus the AP806 MoChi processor.

- AMD's third-generation G-Series and R-Series embedded processors, plus the new Zen CPU core.

- Market-size and vendor-share data for 2015 and 2016.

- Updated market forecast through 2021.

Special Offer:

A corporate-wide license is $5,995, and a single-copy license is $4,495. We can offer a pre-publication discount of $500 off the corporate license or $300 off a single license until April 10, 2017.

The preliminary table of contents is on our web site:
http://www.linleygroup.com/embedded

For more information or to order the report, please email us at cs@linleygroup.com.

Altair LTE Chip Integrates M1, NB1
By Loring Wirbel

Altair Semiconductor hopes to cover the IoT waterfront with its new ALT1250, an LTE baseband device that's compatible with both the Category M1 and Category NB1 standards for low-data-rate communications. The chip is a successor to the ALT1150/1160 line, which the company developed before the 3GPP added new IoT options in LTE Release 13. The baseband/transceiver pairs with an RF front end, the ALT1910, to provide what Altair calls "OneSKU" capability, enabling multiple LTE-band combinations (including FDD and TDD) in one hardware implementation.

The ALT1250 is the first new Altair chipset since the company was acquired by Sony one year ago. True to its promises at the time, Sony has allowed Israel-based Altair independence as a wholly owned subsidiary, and it has invested enough money in product development to ensure several generations of LTE/5G designs for industrial and IoT applications. Altair continues to gain traction with its ALT1160 Cat1 chipset, which serves in a Verizon-certified module by Asiatelco for consumer and industrial IoT products. Ownership by a Japanese conglomerate is no liability. Though Altair's main competitor is the Paris-based startup Sequans, larger players such as Intel and ARM are trying to enter the M1/NB1 market.

Qualcomm's ability to expand its LTE IoT presence will depend in part on its completion of the NXP acquisition and on integration of that company's technology. Intel is a late entrant in this sector, though its LIQD precertification program and its sheer size could make the company a formidable competitor.

Microprocessor Report subscribers can access the full article:
http://www.linleygroup.com/mpr/article.php?id=11771

Arteris Piano Tunes Timing
By Mike Demler

The Physical Interconnect-Aware Network Optimizer (Piano) 2.0 from Arteris offers new features to automate interconnect-timing closure in SoCs that employ the company's network-on-a-chip (NoC) intellectual property (IP). The Piano tools help designers more quickly resolve clock skews and signal delays caused by the resistance, capacitance, and inductance of long on-chip wiring. Those unavoidable parasitic effects can degrade performance and cause malfunctions. Arteris licenses Piano as an optional package for users of its FlexNoC and Ncore products.

The company first addressed the timing-closure problem by releasing FlexNoC Physical, now called Piano. Timing closure typically requires multiple iterations, but Piano shortens that process by calculating a prelayout estimate of wire lengths and their delays, comparing the results with designer-specified constraints. It thus allows users to quickly determine whether the target specifications are even achievable and to identify where pipeline stages are required. The tool's automatic pipeline creation helps users avoid inserting unnecessary register stages. The benefits are smaller die and lower power.

The first Piano only worked with the noncoherent FlexNoC, but Piano 2.0 adds the capability for designers to combine that interconnect with the coherent Ncore NoCs. Arteris also offers interconnect IP that's compatible with ARM's CoreLink products, but ARM's cache-coherent networks lack NoC features and automation tools. The increased productivity that Piano affords will therefore attract many SoC designers to Arteris NoCs instead.

Microprocessor Report subscribers can access the full article:
http://www.linleygroup.com/mpr/article.php?id=11768

Helio X30 Nabs Speed Lead
By Mike Demler

MediaTek has announced its new Helio X30, a tricluster deca-core chip that's the third member of the elite 10nm smartphone-processor club. Unlike its competitors, however, the company is the first to use TSMC's new 10nm technology. It's also the first to employ such an advanced process to integrate premium features in a device targeting mainstream phones that sell for $200-$300.

The new Helio design uses the same arrangement the company introduced in the 20nm Helio X20: 10 CPUs divided into a dual-core "max" cluster, a quad-core "mid" cluster, and a quad-core "min" cluster. Instead of Cortex-A72, the big cores are the more power- and area-efficient Cortex-A73; the little cores likewise change from Cortex-A53 to the smaller and more power-efficient Cortex-A35.

The X30 also shifts gears on the graphics engine compared with its predecessor. It uses a custom quad-core PowerVR Series7XT Plus from Imagination, replacing the X20's ARM Mali-T880 MP4. Other upgrades include an LTE Category 10 baseband that supports three-carrier aggregation on the downlink as well as a dual-camera 16Mpixel ISP that supports 4K video recording and playback, along with 8x slow motion. The ISP gets a boost from Cadence's Tensilica Vision P5 VPU (vision processing unit), which offloads the CPUs and GPUs to handle MediaTek's Imagiq computational-photography system.

The Helio X30 won't set benchmark records, but vendors aiming for those prizes must employ much more expensive custom CPUs along with area- and power-hungry graphics engines. The new top-of-the-line MediaTek processor delivers a balanced and cost-conscious feature mix, which will appeal to consumers looking for a budget-friendly alternative to the latest Apple and Samsung flagship models.

Microprocessor Report subscribers can access the full article:
http://www.linleygroup.com/mpr/article.php?id=11770

Smaller Offspring for TI's Sitara
By Tom R. Halfhill

Bargain hunters will appreciate two additions to Texas Instruments' ARM-based Sitara processor family: the AM5706 and AM5708. Sampling now, they extend the AM57x-series into embedded applications that require lower power, lower cost, and less board space. Like other AM57x processors, they integrate an ARM Cortex-A15 CPU with two Cortex-M4 controller cores, a C66x DSP, and TI's own programmable controller cores. No competing products can match their features for signal processing, floating-point throughput, and real-time control.

Compared with the smallest previous AM57x processors, they reduce the maximum clock speed of the Cortex-A15 CPU by 33%, to 1.0GHz. The C66x DSP core runs at 750MHz as usual, but some models have a 500MHz CPU and DSP.

In addition, the new chips omit the Serial ATA (SATA) and two camera interfaces found on other AM57x chips. The AM5706 also drops the PowerVR SGX544 GPU and VeriSilicon GC320 video-compositor core. Although the AM5708 retains those graphics features, it has only two LCD outputs instead of the three included in other GPU-integrated AM57x chips.

Thanks to these economies, TI says the new chips will typically consume 1.5-3.0W. That's a 14% to 25% reduction. The new products cost less, too: list prices for 1,000-unit volumes are $17-$36, which is 23% to 52% less than existing AM57x chips. Production is scheduled for 2Q17.

Microprocessor Report subscribers can access the full article:
http://www.linleygroup.com/mpr/article.php?id=11772

About Linley Newsletter

Linley Newsletter is a free electronic newsletter that reports and analyzes advances in microprocessors, networking chips, and mobile-communications chips. It is published by The Linley Group and consolidates our previous electronic newsletters: Processor Watch, Linley Wire, and Linley on Mobile. To subscribe, please visit:
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Our previous subscription newsletters -- Microprocessor Report, Networking Report, and Mobile Chip Report -- are now consolidated in a single subscription newsletter: Microprocessor Report. MPR publishes articles with significantly more detail on the subjects covered in our free electronic newsletter. To subscribe, please visit:
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Copyright 2017, The Linley Group

Domain: Electronics
Category: Semiconductors

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