Linley Newsletter: October 12, 2017

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Linley Newsletter

(Formerly Processor Watch, Linley Wire, and Linley on Mobile)

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Issue #569

October 12, 2017


Independent Analysis of Microprocessors and the Semiconductor Industry

Editor: Tom R. Halfhill

Contributors: Linley Gwennap, Loyd Case


In This Issue:

- Centriq Is the King of Cache

- RISC-V U54 Runs Linux

- Imagination Adds Neural-Network IP


Now Available: Processor Conference Proceedings

The Linley Processor Conference was held on October 4 - 5, 2017 at the Hyatt Regency Hotel, Santa Clara, CA. This two-day, dual-track conference featured technical presentations addressing processors and IP cores for deep learning, servers, communications, embedded, and advanced automotive systems. This in-depth technical conference is the industry's premier processor event and hosted several new product announcements. In addition to over 20 technical presentations by experts from the companies leading the industry, the conference program included a keynote session covering technology and market trends in processor design.

If you missed this event, you can download a copy of all slides from all of the presentations. The proceedings are available at no cost to all interested parties. To download the documents, access

http://www.linleygroup.com/events/proceedings.php?num=43


Centriq Is the King of Cache

By Tom R. Halfhill

Qualcomm disclosed more details about its Centriq 2400 server processor at the recent Linley Processor Conference, confirming it’s one of the most powerful ARMv8 designs yet. The 48-core chip, which has been sampling for nearly a year, resembles Cavium’s future 54-core ThunderX2 in many respects but falls short of the best x86 server chips. Even so, it’s an impressive initial effort for a new server-processor vendor to target cloud-service providers.

The Centriq 2400 has 48 of the new 64-bit Falkor CPUs arranged in pairs that share an L2 cache. At the conference, Qualcomm revealed that each L2 cache is 512KB, for a total of 12MB. In addition, the L3 cache comprises twelve 5MB partitions distributed around the internal ring network that connects all the CPUs, caches, memory controllers, I/O interfaces, and other elements. Effectively, the L3 cache is 60MB, so the total L2/L3 cache is 72MB—or 26% more than Intel’s top-end Xeon Scalable server chip.

The company disclosed a few more details about the on-chip ring network. This bidirectional ring enables full coherence among all the CPUs, caches, and I/O controllers. To achieve the target bandwidth of 280GB/s, the ring is actually divided into four 512-bit-wide rings, two in each direction. Ring traffic is divided into 128-byte blocks, matching the size of the L2 and L3 cache lines. The odd and even packets are interleaved across the two parallel rings. Reads are multicast to reduce traffic where possible.

Compared with the first-generation designs from other ARM vendors, the Centriq 2400 is better in several respects, including core count, cache size, and memory bandwidth. It has some innovative (if unproven) features for compressing DRAM bandwidth and optimizing the L3 cache. It’s the first server processor to boldly abandon 32-bit software compatibility, and it’s debuting in a 10nm FinFET process.

Microprocessor Report subscribers can access the full article:

http://www.linleygroup.com/mpr/article.php?id=11870

RISC-V U54 Runs Linux

By Linley Gwennap

SiFive continues to roll out new CPUs, this time delivering its first core with a full memory-management unit (MMU) for Linux and other high-level operating systems. Like its previous cores, the U54 employs a simple five-stage in-order pipeline that can execute a single instruction per cycle. The new MMU allows the company to target low-performance embedded systems that require a full OS, such as smart TVs, broadband gateways, and IoT hubs. Introduced at the recent Linley Processor Conference, the U54 recently taped out; production RTL will be available to customers by the end of the year.

SiFive also disclosed a new “coreplex” that packs four U54 CPUs plus a management CPU based on its E51 design. This design is the company’s first to include multicore support and cache coherence. Each of the main CPUs features 32KB of instruction cache and 32KB of data cache, and they share a coherent 2MB level-two cache. The company will license the CPU and coreplex to SoC and ASIC designers; although the RISC-V instruction set and CPU generator are open source, customers must pay to license a complete, validated, and supported core design. SiFive will develop complete chips for customers as part of its ASIC-design program, too.

The U54 is based on the same basic pipeline as SiFive’s other cores, which originate from the Rocket CPU generator that the company’s founders developed while at UC Berkeley. All integer instructions use a five-stage pipeline that’s similar to early RISC designs. This short pipeline minimizes penalties for mispredicted branches and other hazards. Keeping the design simple reduces die area as well. In general, however, shorter pipelines operate at lower clock speeds, and this design will be limited by its single-cycle cache accesses. SiFive expects the U54 to reach 1.5GHz in TSMC’s 28nm HPC technology.

Microprocessor Report subscribers can access the full article:

http://www.linleygroup.com/mpr/article.php?id=11868

Imagination Adds Neural-Network IP

By Loyd Case

Imagination has joined the growing field of vendors that supply deep-learning accelerators (DLAs) by offering its PowerVR 2NX. The new intellectual property (IP) core provides a scalable architecture that emphasizes integer performance and targets inferencing in mobile and other power-constrained devices. The company plans to deliver production RTL by 4Q17.

The growing interest in deep learning has companies scrambling to develop new architectures for efficient neural-network processing. This market bifurcates into training and inferencing. Whereas training occurs in data centers using power-hungry high-performance GPUs, inferencing is moving to client devices such as automobiles and smartphones. For example, Apple and Huawei now offer neural engines in their newest high-end processors.

Although GPUs are popular for training, most DLAs are based on DSP architectures. Despite Imagination’s GPU roots, its Vision and AI group developed the PowerVR 2NX; the new design is entirely independent of the company’s existing DSP and GPU architectures.

Imagination designed the PowerVR 2NX around a scalable, flexible architecture, much like its GPUs. A single core can have one to eight neural-network compute units, each capable of performing 256x8-bit MACs or 128x16-bit MACs in a single cycle. In addition, the DLA IP differentiates from the competition by offering flexible support for variable-width data. The architecture can pack multiple small data items into a single 16-bit word.

Imagination has been struggling since it announced earlier this year that Apple would be dropping PowerVR for an internal GPU design. It recently sold its MIPS division to Tallwood Venture Capital for $65 million and agreed to sell the rest of the company to Canyon Bridge Venture Capital, which is backed by the Chinese government, for $743 million. These deals should mitigate customer worries about the stability of Imagination and PowerVR.

Microprocessor Report subscribers can access the full article:

http://www.linleygroup.com/mpr/article.php?id=11869

About Linley Newsletter

Linley Newsletter is a free electronic newsletter that reports and analyzes advances in microprocessors, networking chips, and mobile-communications chips. It is published by The Linley Group and consolidates our previous electronic newsletters: Processor Watch, Linley Wire, and Linley on Mobile. To subscribe, please visit:

http://www.linleygroup.com/newsletters/newsletter_subscribe.php

Domain: Electronics
Category: Semiconductors

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