Linley Newsletter: October 24, 2018

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Linley Newsletter

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Issue #623

October 24, 2018

Independent Analysis of Microprocessors and the Semiconductor Industry

Editor: Tom R. Halfhill

Contributors: Linley Gwennap, Mike Demler, Bob Wheeler

In This Issue:

- Arm Frees FPGAs to Use Cortex-M

- IBM Power9 Scales Up in Servers

- Intel 9th Generation Adds Little

Linley Fall Processor Conference

Free On-Line Registration Ends Tomorrow

On October 31 and November 1, The Linley Group will host the Linley Fall Processor Conference at the Hyatt Regency Hotel in Santa Clara, California. This in-depth technical conference is the microprocessor industry's premier event, covering the latest processors, memory, and IP cores used in deep learning, embedded, communications, automotive, IoT, and server designs. The program includes 29 technical presentations by experts from the companies leading the industry, including these keynotes:

Day One - October 31 - 9am

"Breaking New Bottlenecks in Processor Design"

Linley Gwennap, Principal Analyst, The Linley Group

Day Two - November 1 - 9am

"Codesign in Google TPUs: Inference, Training, Performance, and Scalability"

Cliff Young, Engineer, Google AI

The conference will feature at least 12 new product and technology announcements, including:

- Cornami will disclose details of its novel architecture for AI acceleration that can scale to millions of cores.

- Arteris IP will announce a new version of FlexNoC with its accompanying AI Package.

- Inside Secure will announce a new product that protects data-center links at line rates of 400Gbps and beyond.

- NXP will announce new processors in the LS1028A family.

- Synopsys will disclose details of ARC's Android Neural Networks API.

Also, don't miss our sponsor exhibits and reception at 4:30-6:00pm on Wednesday, October 31. It's a great networking opportunity with sponsors, exhibits, a raffle from The Linley Group, heavy hors d'oeuvres, and an open bar.

For a complete schedule with details on each speaker and presentation, visit our web site:

Admission is free to pre-qualified attendees who register on-line by October 25, 2018. Qualified attendees include system designers, chip designers, software designers, OEM/ODMs, service providers, press, and the financial community. The fee for other attendees is $795 for registrations received on-line.

On-line registration will close on Thursday, October 25 at 5pm Pacific Time. You can also register on-site at the event for a fee of $195 for qualified attendees and $995 for non-qualified.

Arm Frees FPGAs to Use Cortex-M

By Bob Wheeler

Striking back against RISC-V, Arm is enabling free use of certain Cortex-M CPUs in Xilinx FPGAs, even for volume production. The new DesignStart FPGA program offers Cortex-M1, an FPGA-optimized version of Cortex-M0, and the general-purpose Cortex-M3.

Given that some Xilinx UltraScale+ models integrate Cortex-A53 and Cortex-R5 hard cores, the new M1/M3 cores will serve primarily in lower-cost 28nm Spartan-7 and Artix-7 designs. They can run an RTOS for real-time control functions or serve embedded management functions.

Introduced in 2006, Cortex-M1 is a simple CPU designed for microcontrollers and conforms with the Arm v6-M instruction set, which is a subset of v7-M. To minimize logic-cell use, it employs the FPGA's multiplier blocks -- part of the DSP slice -- for ALUs and other functions. Another mature design (dating to 2004), Cortex-M3 is the precursor to the newer Cortex-M4 and Cortex-M33. It implements the Arm v7-M ISA. Arm plans to release the Xilinx-targeted M3 at the end of October, at which time further details will be available. It intends Cortex-M1 for simple control and management functions, whereas the M3 can serve as the main CPU in various embedded and IoT applications.

Arm says the existing DesignStart programs have led to more than 3,000 downloads and 300 commercial licenses in the last 12 months. DesignStart FPGA lowers the barrier further by removing royalties, helping it protect its ISA against encroachment by RISC-V. Because most existing customers will want newer designs like Cortex-M33 and Cortex-A55, the company can afford to use dated cores to combat RISC-V's growing developer mindshare.

Microprocessor Report subscribers can access the full article:

IBM Power9 Scales Up in Servers

By Tom R. Halfhill

IBM says the 12-core Power9 processor for scale-up servers is now available on the merchant market to system vendors and manufacturers. This model accesses DRAM through external buffer chips, which provide industry-leading memory bandwidth and capacity for enterprise servers that handle large workloads. It also offers industry-leading per-core integer throughput, I/O bandwidth, and glueless symmetric multiprocessing (SMP).

By contrast, the scale-out Power9 processors that have been shipping for about a year integrate standard DDR4 DRAM controllers. They provide less bandwidth but are better suited to lower-cost systems (such as web servers) that handle threads with modest memory requirements. By offering Power9 products with both types of memory subsystems, IBM is targeting a wide range of servers with the same basic chip design.

The scale-out (SO) models have been shipping since 4Q17 (24 cores) and 1Q18 (12 cores). Initially, they appeared in IBM's own Power servers and in a pair of supercomputers (Summit and Sierra) at the Oak Ridge and Lawrence Livermore national labs. Those machines currently rank first and third on the Top500 list. Other Power9 customers are OpenPower Foundation members such as Foxconn, Inspur, Inventec, Raptor, Supermicro, and Wistron. Most are Chinese vendors of servers or boards; IBM says additional announcements are pending.

Power9 offers the best per-core performance of any server processor. On the SPEC CPU2017 benchmarks, a dual-socket system with 12-core processors easily beats AMD and Intel dual-socket systems that have equal or greater core counts. The new scale-up (SU) model provides exceptional system-level performance for in-memory databases and other big-data applications that can exploit its superior memory subsystem. High-performance computing (HPC) is another strength, as the Top500 scores testify. But the older SO models remain attractive for data-center customers wanting a more economical and power-efficient server processor that delivers the same per-core performance.

Microprocessor Report subscribers can access the full article:

Intel 9th Generation Adds Little

By Linley Gwennap

To maintain its annual marketing cadence, Intel rolled out its first 9th Generation processors despite having no new microarchitecture or process technology to boost performance. Unsurprisingly, the result was underwhelming. Almost all the new products, which target gamers and content creators, offer minimal performance upgrades at the same or higher price than their predecessors.

The most interesting new product is the Core i9-9900K, the first eight-core processor in the S-series. The extra cores come with L3-cache slices, expanding the L3 to 16MB. Based on the Coffee Lake-S Refresh design, it's the first Intel PC processor with hardware mitigation for certain side-channel attacks. The maximum turbo frequency is 5.0GHz, matching the top speed of the recent Core i7-8086K. We estimate the performance gain over the 8086K is 4-5% for most games, but the 9900K costs about $60 more.

The new Core i7-9700K enables eight cores but only eight threads and 12MB of cache; we estimate this 8/8 configuration will perform similarly to the older Core i7-8700K's 6/12 configuration on most games, although the small clock-speed boost could help a bit. The Core i5-9600K is essentially identical to the Core i5-8600K, offering a 6/6 configuration and 9MB of cache but slightly higher speeds.

The new X-series products are based on the same Skylake-SP microarchitecture as the earlier products, but in the newer 14nm++ process. As such, they lack any new features or capabilities other than better thermal paste. For example, the top-end Core i9-9980XE provides the same core count and price as the older Core i9-7980XE while offering a modest base- and turbo-speed boost. A similar boost applies to the lower-core-count models. For those having 14 or fewer cores, Intel had to raise the TDP from 140W to 165W to handle the faster clock.

Microprocessor Report subscribers can access the full article:

About Linley Newsletter

Linley Newsletter is a free electronic newsletter that reports and analyzes advances in microprocessors, networking chips, and mobile-communications chips. It is published by The Linley Group. To subscribe, please visit:

Domain: Electronics
Category: Semiconductors

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