Linley Newsletter: September 20, 2018

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Linley Newsletter

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Issue #618

September 20, 2018

Independent Analysis of Microprocessors and the Semiconductor Industry

Editor: Tom R. Halfhill

Contributors: Linley Gwennap, Mike Demler, Bob Wheeler

In This Issue:

- DeePhi Accelerates Xilinx AI Strategy

- Graphcore Makes Big AI Splash

- Wear 3100 Boosts Smartwatch Life

- Broadcom First With 200Gbps NIC

The Linley Fall Processor Conference 2018

Program Available Now!

October 31 and November 1, 2018

Hyatt Regency Hotel, Santa Clara, California

The program for our fall conference is now available, and FREE registration for qualified attendees is open!

This two-day, partially dual-track conference features technical presentations on processors for communications, IoT, servers, and advanced automotive systems. This in-depth technical conference is the industry's premier processor event, and we expect several new announcements. In addition to 27 technical presentations by experts from industry-leading companies, the program will include a keynote session covering technology and market trends in processor design.

The Fall Processor Conference is our largest event and includes presentations on the latest processor chips, processor IP, and other technologies required to efficiently process packet, sensor, and vision data. It's for chip designers, system designers, equipment vendors, OEM/ODMs, service providers, press, and the financial community.

Sponsors: Synopsys, Arm, Micron, Rambus, Imagination Technologies, Netspeed Systems, Arteris-IP, Cadence, CEVA, Andes Technology, Inside Secure, SiFive, SecureRF, GlobalFoundries, NXP, Efinix, Mellanox Technologies, Wave Computing, AiMotive, Qualcomm, FlexLogix, Netronome, and the MIPI Alliance.

Click here for more information:

DeePhi Accelerates Xilinx AI Strategy

By Mike Demler

Xilinx recently acquired DeePhi, a developer of FPGA-based accelerators for computer vision and speech recognition. DeePhi developed two different neural-network inference engines, which it delivers preinstalled on a family of Zynq-powered PCIe cards. The Aristotle architecture targets convolutional neural networks (CNNs), and Descartes is for recurrent neural networks (RNNs) that use long-short term memory (LSTM).

DeePhi integrates Aristotle on its DP-2400 video cards, in various configurations that come with software for advanced driver assistance system (ADAS), face analytics/tracking, video surveillance, and other applications. Descartes powers the company's speech-recognition engine. Customers can access the Descartes technology on Amazon's web service (AWS) and Huawei's cloud platform.

The DeePhi designs fit Xilinx's plan to offer a library of soft-overlay architectures for its FPGAs, including the next-generation 7nm Everest products. The overlays don't eliminate the need for HDL-based design, but they offers a much shorter time to market (or at least to prototype) than using licensed IP cores to build an ASIC. The success of the overlay program will depend on competitive application-specific IP designs developed by experts such as DeePhi, along with software tools that make integration easier than traditional FPGA design flows.

Microprocessor Report subscribers can access the full article:

Graphcore Makes Big AI Splash

By Linley Gwennap

Graphcore's much anticipated first product is a powerful processor that aims to loosen Nvidia's firm grip on deep-neural-network (DNN) training in large data centers. Starting from a blank page, the British company created a new AI-specific architecture, which it calls the IPU (intelligence processing unit), that packs more than a thousand programmable cores onto a single massive chip. The result is a highly flexible design that generates as many floating-point operations (flops) as Nvidia's V100 at less than half the power.

Graphcore claims its performance advantage will be greater across a broad range of neural networks thanks to the IPU's large on-chip memory and other unique features. The first IPU chip, called the GC2, is already sampling and is scheduled for production by the end of this year.

At $112 million, Graphcore is one of the best-funded AI-chip startups. Sequoia, a top venture-capital firm, has invested $50 million; strategic investors include Bosch, Dell, and Samsung. Graphcore has 116 employees and two dogs, most at its Bristol, U.K., headquarters plus a handful at its rapidly expanding Silicon Valley office.

The GC2 supports FP32 and FP16 data formats, similar to Nvidia's V100, making it well suited to DNN training. It can also perform inferencing, but most inference tasks are shifting to more-efficient integer formats that run well on CPUs and ASICs such as Google's TPU1. Whereas GPUs rely on a host CPU to handle certain DNN layers, the IPU can handle all layers, increasing efficiency by avoiding data transfers to the host. Graphcore will sell GC2-based accelerator cards to Dell and other system vendors; these cards will generate up to 250Tflop/s at a 300W TDP -- twice the performance of a V100 card at a similar power. The startup offers ONNX and TensorFlow drivers, easing the implementation of DNNs on its chip.

Microprocessor Report subscribers can access the full article:

Wear 3100 Boosts Smartwatch Life

By Bob Wheeler

Qualcomm's answer to longer smartwatch battery life is big-small-tiny. The company's new Snapdragon Wear 3100 platform adds a "tiny" real-time controller to augment the main processor's "big" quad Cortex-A7 CPUs and "small" Hexagon DSP. The new architecture combines Wear OS running on the main processor with an RTOS running on the new QCC1110 controller. It also splits Qualcomm's smartwatch platforms, with the Snapdragon Wear 3100 (SDW3100) serving Wear OS designs and the recent Snapdragon Wear 2500 targeting kid watches and Android designs.

Adding the QCC1110 controller also creates a dual-mode smartwatch -- one that can run Wear OS in normal operation but shift into an RTOS-only mode to extend battery life. A customer could, for example, design the watch to shut down Wear OS when the battery charge falls below 20%, allowing the watch to offer limited functions until it can be recharged. After all, who wants to pay $250 for a wrist weight?

Aside from adding the QCC1110, the SDW3100 chipset is identical to the SDW2500. It includes the MSM8909w main processor, QCC1110 controller, PMW3100 power-management IC (PMIC), WCN3620 Wi-Fi/Bluetooth combo, and optional GPS or combo cellular/GPS transceivers. For cellular designs, Qualcomm's GaAs power amplifiers reduce power dissipation compared with the CMOS devices in the prior-generation Snapdragon Wear 2100. For mobile payments, the 3100 platform includes an optional NQ330 NFC chip from NXP.

Qualcomm has more than an 80% share of Wear OS devices, so it must expand the Wear OS market to expand its wearables business. In smartwatches, its planned trifecta includes adding Android-phone OEMs, luxury/fashion brands, and sports specialists. Reducing power dissipation is paramount to increasing adoption, enabling more user interaction and better industrial design balanced with acceptable battery life.

Microprocessor Report subscribers can access the full article:

Broadcom First With 200Gbps NIC

By Bob Wheeler

Broadcom is first to sample Ethernet adapters for new 50Gbps-per-lane standards, including 50GbE and 200GbE. The NICs use the new Thor controller chip, the company's third-generation NetXtreme-E design. The PAM4-based network ports work with switch systems that support the new Ethernet standards, such as those based on Broadcom's Tomahawk 3 or Innovium's Teralynx. By moving from 25Gbps NRZ to 50Gbps PAM4, Thor doubles the bandwidth per lane in a server connection, reducing the cost of 50GbE and 100GbE ports while offering 200GbE for the first time.

The controller chip enables new NetXtreme-E adapters including the P2100G PCIe NIC with dual 200Gbps ports and the M1100G OCP mezzanine Type II adapter with a single 100Gbps port. It builds on Stratus, Broadcom's 100GbE controller, which achieved first customer shipments in 4Q17. Like its predecessor, Thor handles the RoCE protocol for low-latency networks. It is Broadcom's first to enable PCIe Gen4, which is supported by IBM's Power9 servers as well as AMD's next-generation Epyc processors (code-named Rome).

Mellanox's ConnectX-6 EN is the only announced 200GbE competitor, and it reached customers shortly after Broadcom's new NICs. The two competitors offer similar features for mainstream data-center applications. The companies already compete in 25GbE NICs; Broadcom gained share in 2017, eating into Mellanox's early lead. The “Super 7” cloud-service providers will be early adopters of 50Gbps-per-lane adapters, pairing them with switches that enable 400GbE leaf-spine architectures.

Microprocessor Report subscribers can access the full article:

About Linley Newsletter

Linley Newsletter is a free electronic newsletter that reports and analyzes advances in microprocessors, networking chips, and mobile-communications chips. It is published by The Linley Group. To subscribe, please visit:

Domain: Electronics
Category: Semiconductors

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