Linley Wire: December 2, 2014

 weSRCH's Best of the Internet Award

Linley Wire

Volume 14, Issue 19

December 2, 2014

Please feel free to forward this to your colleagues

Independent Analysis of the Networking-Silicon Industry

Editor: Bob Wheeler

Contributor: Loring Wirbel and Jag Bolaria

In This Issue:

- Marvell Enters Search-Engine Market

- Xilinx’s SDAccel Goes Heterogeneous

- Tabula Changes Validation Rules

Save the Date!

The Linley Data Center Conference 2015

February 25-26 in Santa Clara

Registration Opens January 8

Cloud computing is exploding and the industry is grappling with an accelerating pace of technology innovation. Hyperscale data centers are breaking the traditional definitions of servers and networking while rapidly scaling performance. The rest of the industry is to trying to keep up, with vendors at all levels shortening development cycles and attempting to standardize new protocols and APIs. For help sorting all this out, mark your calendar for the Linley Data Center Conference coming to the Hyatt Regency Hotel in Santa Clara on February 25-26.

Attendees can meet with industry leaders and The Linley Group analysts, network with peers, attend an evening reception with sponsored exhibits and demos, and more. Program details will be announced soon. Check our web site for updates:

Marvell Enters Search-Engine Market

By Loring Wirbel

Marvell is sampling a network search engine (NSE) with a unique SRAM-based design using patents from Questarium, a company it acquired in 2011. The 160Mb Questflo 98TX1100 employs elements of TCAM- and algorithm-based NSEs, using a hash operation to choose RAM lines and thus avoid activating an entire memory array during a search. The hash selection is one of many proprietary power-saving features.

The 600MHz 98TX1100 can perform four operations in parallel, enabling a maximum of 2.4 billion decisions per second. It can scale to eight million flow entries by cascading multiple devices. The processor can search a variety of table types, such as source-address tables, routing tables, ACLs, and NAT tables. Once configured, Questflo oversees table and resource management without user intervention.

In addition to eight modified SRAM blocks, the device integrates a key-generation unit and parallel deterministic search engines, as well as a dual-port Interlaken-LA interface, a Cascade interface, and 24x12.5Gbps serdes for both of these interfaces. Users can select table configurations and search widths, allowing one Questflo device to perform multiple search types.

We believe Broadcom’s NLA12000 will be the most direct competitor to Marvell’s Questflo, given that both claim 2.4 billion searches per second and offer 24 bidirectional serdes lanes running at 12.5Gbps. Whereas Broadcom’s chip is in production, however, Questflo implements new and unproven technology. To break Broadcom’s near-monopoly in NSEs, Marvell must prove its technology can match the performance of traditional TCAM.

Networking Report subscribers can access the full article here:

Xilinx’s SDAccel Goes Heterogeneous

By Loring Wirbel

Xilinx has emphasized its interest in OpenCL by releasing new software that eases FPGA development for heterogeneous-compute environments. The company is touting its SDAccel (Software-Defined Development Environment for Acceleration) tool as being particularly useful in data centers, where accelerator cards that aid CPUs or GPUs with tasks such as encryption must meet strict power budgets of 25W or less.

Xilinx’s common developer environment for heterogeneous computing involves a three-step compilation process. OpenCL defines each hardware accelerator for a compute task as a “kernel,” which differs from an OS-level kernel. Designers first define, compile, and emulate an accelerator kernel on an x86 host, with initial verification and debugging taking place on the host. They then compile and co-simulate the optimized kernel with other kernels in System C on the host. Only in the third and final step is the kernel compiled for execution on a chosen FPGA device. This process allows several design iterations without committing to back-end steps such as place and route.

Few products compete directly with SDAccel. CPU and GPU compilers—even parallel tools such as Nvidia’s Cuda—lack straightforward hooks for adding compiled accelerators implemented in FPGAs. Altera is the only other FPGA vendor committed to OpenCL, yet its current design flow treats CPU/GPU compilation and FPGA-based accelerator-kernel compilation as two distinct steps, offering no common environment.

Networking Report subscribers can access the full article here:

Tabula Changes Validation Rules

By Jag Bolaria

Tabula has developed a groundbreaking process that can access every node and signal in its 3D programmable logic devices (3PLDs) to enable complete validation. Moreover, the company is going a step further: its methodology can find bugs in the field. And since its 3PLDs are FPGAs, customers can alter them to fix bugs and add new features. Tabula packages the validation tools in its DesignInsight technology, which works in conjunction with its Abax2 architecture and Stylus compiler to deliver the same level of 3PLD access and flexibility in the lab or in the field.

Each 3PLD time slice in the Abax architecture is configured in real time, so the same logic can also monitor each node in real time. DesignInsight consists of hardware and software suites that Tabula integrates in its Stylus RTL compiler. It uses the concept of a “view” to capture specific traces in the Abax programmable logic. Each view captures the device state when triggered by a user-specified condition. The user can set up multiple views in sequence to examine a design’s internal operations.

Combined with the ability to rapidly change the design to correct system problems in the field, DesignInsight provides a huge safety net, enabling customers to deploy products with greater confidence. This flexibility gives Abax an advantage over other FPGAs, particularly for leading-edge and evolving technologies. System designers can target new standards and specifications with the assurance that they will be able to adapt their designs to meet final requirements.

Networking Report subscribers can access the full article here:

About Linley Wire

Linley Wire is a free electronic newsletter published by The Linley Group, a technology analysis and strategic consulting firm. Linley Wire will present our analysis of recent news on semiconductors for networking and communications. Articles are posted weekly to our web site and sent monthly via email. To access the web content directly, visit our web site.

Linley Wire is not affiliated with any outside vendors. We do not rent or sell our mailing list; it is used only to send you the newsletter and information on our events.

We encourage you to forward this newsletter to colleagues who may benefit from receiving this information. They may subscribe by visiting our web site.

Domain: Electronics
Category: IT
weSRCH App on Apple

Recent Newsletters

Linley Newsletter: August 8, 2019

Linley Newsletter Please feel free to forward this to your colleagues Issue #664 August 8, 2019 Independent Analysis of Microprocessors and the Semiconductor Industry E

08 August, 2019

Linley Newsletter: August 1, 2019

Linley Newsletter Please feel free to forward this to your colleagues Issue #663 August 1, 2019 Independent Analysis of Microprocessors and the Semiconductor Industry E

01 August, 2019

Linley Newsletter: July 25, 2019

Linley Newsletter Please feel free to forward this to your colleagues Issue #662 July 25, 2019 Independent Analysis of Microprocessors and the Semiconductor Industry

25 July, 2019