Linley Wire: July 29, 2015

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Linley Wire
Volume 15, Issue 12
July 29, 2015

Independent Analysis of the Networking-Silicon Industry

Editor: Bob Wheeler
Contributors: Tom R. Halfhill, Loring Wirbel, Bob Wheeler

In This Issue:

- Cavium Secures the Cloud
- Freescale Overhauls the Data Plane
- QorIQ Chips Add More ARMs
- Sckipio Unites G.fast and PON in SFP
- Mellanox Bets on 25G, 50G Ethernet

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Cavium Secures the Cloud
By Bob Wheeler

The long-time market leader for security coprocessors, Cavium is protecting its turf by introducing its next-generation Nitrox design. The new chip comes at a time when cloud-service providers are encrypting an increasing proportion of web traffic. Their customers are also encrypting more traffic in multitenant data centers. Purpose-built coprocessors help scale encryption performance more efficiently than server processors (e.g., Xeon) using x86 instructions. Although the security-coprocessor market remains small, it isn’t going away.

Sampling this quarter, Nitrox V delivers impressive performance for three distinct functions: public-key crypto, bulk-data crypto, and data compression. In the first category, it provides at least three times the SSL performance of the leading competitor as well as Cavium’s prior-generation Nitrox III. (Because Nitrox III is actually Cavium’s fourth-generation design, the company skipped the “Nitrox IV” designation). Nitrox V offers up to 100Gbps of throughput for IPSec, which is the most demanding bulk-crypto application. It also handles up to 100Gbps of data compression, for which there are multiple applications.

Getting all of this data into and out of the chip requires fast interfaces. Nitrox V sports a pair of PCIe Gen3 x8 interfaces, each of which can connect with a host processor such as an Intel Xeon or Cavium Octeon. To provide virtual machines (VMs) with direct access to acceleration, each PCIe interface offers SR-IOV with 128 virtual functions. For embedded designs, particularly for IPSec, the chip provides a pair of Interlaken interfaces.

Cavium remains committed to Nitrox owing to the steady demand for these niche coprocessors. Hyperscale-data-center operators are increasing their use of acceleration or offloads to reduce cost and power relative to using server processors for everything. Nitrox V provides the greatest power efficiency for encryption, which is a well-defined application suitable for purpose-built silicon.

Networking Report subscribers can access the full article here:
http://www.linleygroup.com/mpr/article.php?id=11438

Freescale Overhauls the Data Plane
By Tom R. Halfhill

Freescale is extensively overhauling its Data Path Acceleration Architecture (DPAA), a blanket term for the specialized packet-processing logic in QorIQ chips. Although the company announced DPAA2 last year, the full scope became clear during training sessions at the recent Freescale Technology Forum in Austin. DPAA2 is a major revision of the data plane that is more powerful, more flexible, and more programmable than the company’s previous designs.

DPAA2 was inspired by Nokia’s Open Event Machine, a model for nonblocking data-plane processing that supersedes conventional thread-based models in multicore processors. The industrywide OpenDataPlane initiative is loosely based on Open Event Machine and is promoted by Linaro, a consortium that develops open-source Linux software for the ARM architecture. OpenDataPlane also supports the Power, MIPS, and x86 architectures, and Freescale is implementing DPAA2 in all of its QorIQ processors, not just the ARM chips.

DPAA2 will debut in the QorIQ LS2085A and LS2045A, a pair of ARM-based communications processors that began sampling in 1Q15. It will also appear in the LS1088A and LS1048A as well as future Power Architecture and ARM chips.

Freescale hopes to achieve several goals with DPAA2. By offloading more tasks from the CPUs, the data-plane hardware improves performance and consumes less power and silicon than the ARM or Power CPUs would require for a pure software implementation. In addition, the abstract programming model enables Freescale to implement DPAA2 in different ways, such as omitting the regular-expression engine in the lower-end L1088A and LS1048A chips. DPAA2 thus enables QorIQ designs that are smaller, cheaper, and more power efficient than before.

Networking Report subscribers can access the full article here:
http://www.linleygroup.com/mpr/article.php?id=11435

QorIQ Chips Add More ARMs
By Tom R. Halfhill

Freescale is expanding its QorIQ family by adding the most powerful members of the LS1 series announced to date. The new LS1048A and LS1088A have four or eight ARM Cortex-A53 cores operating at 1.5GHz—plus the company’s much-improved packet-acceleration hardware.

At its recent technology forum in Austin, Freescale also made two important roadmap announcements: future LS2-series processors will use the more-muscular Cortex-A72 core, and the Power Architecture branch of the QorIQ family will advance to 16nm FinFET technology. Some of those 16nm PowerPC chips will be shrinks of existing 28nm T-series designs, and others will be fresh designs.

Although the new eight-core LS1088A and quad-core LS1048A aren’t the first LS1-series chips to use Cortex-A53 CPUs, the LS1088A is the first to have more than four cores. These new chips are designed mainly for intelligent network-interface cards (NICs) and edge routers, and they are also useful for industrial and aerospace applications. They have dual 10 Gigabit Ethernet (10GbE) ports, eight GbE ports, cryptography engines, and Freescale’s second-generation packet-acceleration hardware (the Data-Path Acceleration Architecture, or DPAA2).

Freescale plans to sample the LS1088A and LS1048A in 1Q16 and begin production in 2H16. These devices will bring new features and performance to the QorIQ LS1 series while staying within its low power and price boundaries. They also offer new ARM alternatives to existing QorIQ Power chips while preserving the differences between the LS1 and higher-performance LS2 series.

Networking Report subscribers can access the full article here:
http://www.linleygroup.com/mpr/article.php?id=11433

Skipio Unites G.fast and PON in SFP
By Loring Wirbel

G.fast, the latest ITU standard for ultrafast broadband over copper, appears to have little in common with the small-form-factor-pluggable (SFP) standard for optical modules. Yet startup Sckipio, an early G.fast pioneer, considered the transceiver module important enough to design a single-port customer-premises version of its G.fast chipset (both analog and digital front ends) to fit in an SFP module.

The startup’s intent is to decouple the residential gateway and network line interface from the service provider’s infrastructure, allowing customers to develop common gateways for xPON and G.fast. In service-provider PON topologies, passive fiber provides a distribution medium to the node, with twisted pair connecting the node to the home. This approach allows service providers to deliver most of the speed advantages of true FTTH while avoiding the trenching and right-of-way problems associated with bringing fiber all the way to the residential gateway. Chip-level technologies that ease the transition from xDSL media to PON-based G.fast reduce the cost to carriers of driving fiber deeper into the network.

Sckipio has developed three separate reference designs for customer premises equipment, the first of which uses the SFP module. The CP1020-EVM bridge employs SFP cages in PON residential gateways to quickly add G.fast support. The CP1010R-EVM implements standard G.fast CPE bridge functions along with reverse power injection. The CP1010-EVM bridge is a cost-optimized reference design for adding CP1000 G.fast CPE chips to inexpensive residential gateways.

Although support for multiple network-side physical media was always a company goal, Sckipio has increased the flexibility of both its distribution-point and CPE silicon to work with a variety of service-provider topologies. Competitors participating in CPE designs, including Broadcom and Realtek, are concentrating more on low-cost hard-wired options to speed G.fast deployment.

Networking Report subscribers can access the full article here:
http://www.linleygroup.com/mpr/article.php?id=11431

Mellanox Bets on 25G, 50G Ethernet
By Loring Wirbel

Mellanox is going broad and deep in data-center switches by diverting from its Switch-X family to launch the high-end Spectrum. This new Ethernet switch delivers port speeds of 10Gbps, 25Gbps, 40Gbps, 50Gbps, and 100Gbps. The 25Gbps speed is the topic of a just-approved IEEE study group, 802.3by, while the 50Gbps speed remains under consideration by way of a special IEEE 802 approval process. Mellanox is thus responding to early OEM demands for two sub-100Gbps speeds that have yet to become 802.3 draft standards.

The company’s heavy InfiniBand (IB) presence provided an early edge in 56Gbps FDR IB for Switch-X, followed by the 100Gbps EDR rate in Switch-IB, which arrived in 2Q14. Therefore, the granularity of 25Gbps and 50Gbps ports is no great surprise. Still, the sheer number of speeds indicates the company wants to address the interests of server and switch manufacturers upgrading from both 10G and 40G Ethernet.

For the server end, the company simultaneously updated its Ethernet adapter line with the ConnectX-4 Lx, a four-speed NIC intended to upgrade 10Gbps adapters with a mix of 10Gbps, 25Gbps, 40Gbps, and 50Gbps ports. Perhaps as unique as its speed varieties is the adapter family’s multihost technology, which allows a single adapter to serve multiple compute and storage hosts. This host multiplexing comes in a standard PCI Express form factor or in a new module-based format developed by the Open Compute Project (OCP).

The company claims Spectrum is the industry’s only true cut-through nonblocking 100GbE switch. Although the product delivers impressive port-to-port latency of less than 300ns as well as 3.2Tbps aggregate throughput, we think its advantages relative to high-end competitors like Broadcom’s Tomahawk are overstated. It offers the best metrics on several fronts, but its advantages in handling real-world traffic are less clear than Mellanox suggests.

Networking Report subscribers can access the full article here:
http://www.linleygroup.com/mpr/article.php?id=11428

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Domain: Electronics
Category: Semiconductors

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