New Breakthrough Non-Volatile Scalable Memory Chip Architecture

 JoAnne Leff
  18th-Jan-2008

New Breakthrough Non-Volatile Scalable Memory Chip Architecture: For Full Range Of Data Storage Applications

Exclusive Marketing Agent:

J. L. Associates

Attn: JoAnne Leff

56 West 84th Street

Ground Floor Suite (212) 874-2835

New York, NY 10024 jo-anne1@ix.netcom.net

Executive Summary

January 15, 2008

Summary:

Carnegie Mellon faculty has validated the level and import of this new breakthrough storage technology after conferring at length with the lead inventor, Joseph Ashwood. Their following statements give credence to the superlatives attached to this new technology:

“With cleverly designed architecture, this new technology enables parallel data storage and access on a single non-volatile memory chip. The scalability created by this technology provides superior speed in accessing and storing data with high storage capacity at a single chip level. With on-chip power management, the technology is truly enabling for applications that requires on-chip high speed data transfer for various high capacity non-volatile memory devices. With the recent advancement of FLASH memory technology and phase-change memory technology, this invention arrives so timely. The rapid increase of data storage capacity presents urgent needs for high speed data access capability that this innovative technology provides.

It is indeed very technologically sound. It enables the scalability of memory storage capacity in a memory device, which is critical for places where large non-volatile storage capacity is required. The present conventional memory technology does not have such scalability.

It has been predicted by many people, such as Gorden Bell, that by 2015, personal devices such as PDA and cell phone needs to have a non-volatile storage of at least 1 T-bytes capacity. This memory technology invention provides a solution to meet that need. It is NOT an opportunistic technology for catching a short temporal time-window. Rather, it is a solution to enable the future.”

In addition, please review the recently published (1/14/2008) “latest news/technology” EETimes article written by R. Colin Johnson, titled "Memory goes multicore" on this new memory chip architecture (refer to Attachment A).

For background purposes it should be established that:

· No current storage technology provides very fast data transfer speeds (GB/sec) at a reasonable cost.

· No current storage technology provides high “volumetric density” (data storage per volume of space >1 TB/cubic inch).

· No current storage technology provides scalability (in terms of lithography and capacity as well as speed).

· No current storage technology provides concurrency capability on a single drive level.

What is needed is a storage technology that can provide all the above in addition to:

· power consumption that is economically viable,

· solid-state durability, and

· the capability to meet the ever increasing demands of data storage in the future.

This new memory chip architecture, which we will also label the “new storage technology,” does, in fact, fulfill all of the above needs, some of which are features unique to only this new technology in addition to other features that are actually introduced by this technology.

At the core of this invention is a new breakthrough memory chip design that introduces, for the first time, the following unique capabilities: concurrency capability (the capability to perform different operations simultaneously) on a single drive level as well as on a single memory chip level. Prior to this invention, the capability to perform concurrent operations did not exist on a single drive level, much less on a single chip level. Also introduced is the capability to scale (in terms of lithography and capacity as well as speed), and the capability to enjoy the fastest data transfer rates for a fraction of current size and cost of device (32 GB/s per 2 TB in a form factor less than 2 cubic inches, which is a tiny fraction of the size and cost of a 1 TB DRAM SSD that offers only 24 GB/s in a form factor the size of a standard refrigerator)—all new capabilities which create important, far reaching ramifications for the full range of data storage applications.

Other important features of this new storage technology are outlined in the following segment. In sum, it would seem that this new memory chip architecture has the capability to open the door to a completely new level of consumer device and networked storage that simply does not exist now.

Product Description & Technology:

This new data storage technology involves a breakthrough memory chip architecture that creates a data storage device that includes non-volatile memory to the extent desired, can be solid-state or MEMS-based, can store 1 TB of data in less than 1 cubic inch, has the rewrite capability of 500 times that of Flash, and can scale down to 8 bits and up to exabytes, yottabytes and beyond. Further, this new storage technology introduces an entirely new and additional level of performance in the form of concurrency of operations (the capability of different operations to be performed simultaneously) on both the single drive level as well as on the single memory chip level. Allow me to emphasize that prior to this invention, concurrency of operations did not exist on the single drive level, much less on the single memory chip level. Note that this new storage technology has data access times that can be significantly less than 1 ms, and a data transfer speed with a concurrency of operations capability in full power mode of up to 512 times that of Flash per TB, and 189.6 times the speed and 512 times the concurrency capability of HDDs per TB with a throughput of 16 GB/s per TB – a data transfer speed that increases with added capacity in contrast to Flash, which has a data transfer speed that decreases with added capacity.

The unique concurrency along with the unique scalability of this new storage technology in combination with its significantly higher data transfer rates, which at 16 GB/s per TB become increasingly faster with capacity, bear illustration. For example, a small data center with a 25 TB capacity utilizing this new storage technology would enjoy the data transfer speed of 400 GB/s and a concurrency of operations capability of 12,800 different operations performed simultaneously as compared to the current technology of choice in such cases, HDDs, with a data transfer speed of a mere 3.29 GB/s and a maximum concurrency capability of only 25 to 30 simultaneous different operations for that same 25 TB data center. Imagine the speed and concurrency of operations available with this new storage technology in place of HDDs when applied to a typical, large 400+ acre performance competitive data center the likes of which Google, Microsoft, etc. build.

Further, in terms of viability, this new storage technology is designed to use currently well developed, proven components with scientific principles that are well understood to implement such a scalable storage device as a chip, a multi-chip package (MCP), or as part of a System-on-a-Chip (SoC), integrating this data storage device with other devices in a single logical package. The fact is, a chip maker could roll out a working prototype in just 3 months time.

In addition, not only does this new storage technology scale, but it also has the entirely unique capability to absorb and utilize the advantages of any new storage technology that “comes down the pike” and becomes viable in the future including PRAM, MRAM, etc., etc. The singularly unique combination of these capabilities insures the longevity and viability of this new storage technology for an exceptionally prolonged period of time in a field that moves with ever increasing rapidity. It should be noted that in terms of the discussion regarding the miniaturization limits of transistors, this new storage technology can, in fact, extend the useful life of a lithographic node due to its enormously increased bandwidth in contrast to any current storage technology.

With all of its advantages, the production cost of such a new data storage device can certainly be equal to the cost of Flash per capacity, but due to particular consolidations unique to this new memory chip architecture employed in most circumstances, the production cost will be lower than the cost of Flash per capacity.

In contrast to all other current storage technologies, this new storage technology is well suited for the full range of applications from the largest data centers to the smallest of consumer electronic products. It further seems reasonable to assume that Intel’s new interest in Flash for smaller servers will be replaced by an interest in this new storage technology for such applications. Flash simply cannot compete with this new storage technology in such cases. It should also be stated that the hot trend of virtualization in data centers will only achieve added value by utilizing this new storage hardware invention.

This new storage technology seems to be positioned to add a whole new level of high performance, elite, consumer electronic product—product with real heft in terms of capacity, speed and a level of performance that is only possible with this new storage technology---all within the smallest form factor possible in such product. This applies not only to product that now exists, but also to product that will be modified as well as product that will be created around the unique capabilities of this new breakthrough storage technology.

In terms of the data center market, it should be noted that HDDs are only perceived to be very inexpensive, but in reality, many are not, even initially. Further, the number of disks necessary for any speed requirements in addition to running costs in data centers with any activity make this new storage technology at issue less expensive than HDDs in the end as well in such situations. As a result, this new storage technology also seems to be positioned to replace HDDs for the entirety of the data center market with the exception of archival use. The solid-state and, therefore, rugged and dependable nature of this new storage technology, the unprecedented data transfer rates, and the distinctive concurrency capability of this new storage technology are also key features for such data centers.

Also as a result of the enormously fast data transfer speeds and concurrency capability that this new technology brings to the table, the additional area of highly performance sensitive applications are now also very much in play. These highly performance critical applications utilize the incredibly expensive and large refrigerator-sized DRAM SSDs. Decision makers will now welcome this new storage technology with its clear advantages over DRAM SSDs. Since speed is the reason why people buy DRAM SSDs, and this new technology can beat their speed for a tiny fraction of their size and cost, it seems reasonable to conclude that this new storage technology is positioned to replace DRAM SSDs for such applications.

Further, the breakthrough design elements of this new storage technology enable a level of control over power consumption that is unique to this new technology and is implemented in the design phase. This new data storage technology also uniquely allows for 2 power modes in a data storage device: full power mode and low power mode. Features of full power mode have already been discussed earlier. This extraordinary level of performance with full power mode occurs with data centers, enterprise systems, desktops and some consumer electronic product.

In low power mode, which occurs with battery-operated products, a data storage device utilizing this new storage technology consumes less than 150mW of power with its well-designed on-chip power management, which is unique on a single memory chip level with this invention. Also in low power mode, replacing HDDs with this new technology provides up to 50% improvement in battery life in laptops and up to 1200% improvement in some other consumer electronic products.

In terms of the “hand-held” consumer electronic product market, which encompasses all cell phones, PDAs, the iPod family, etc., low power mode is in play. It can be argued that Flash is the storage technology of choice in this market due to its small form factor capability with some HDD use—until now. Any device that utilizes this new storage technology will not only enjoy the smallest form factor per capacity with the highest volumetric density, but it will also enjoy 4 times the speed of Flash as well as 4 times the concurrency capability of Flash in low power mode, and up to 9 times the speed and 4 times the concurrency capability of the HDDs employed in these hand held consumer electronic products in low power mode utilizing the usual Li-ION battery. Having said that, since a relationship exists between performance and power that can be customized in the design phase of this new storage technology, these performance ratios can certainly be increased. In addition, with the future launch of Microturbine batteries or Hydrogen fuel cells, more than enough power will be available to replace low power mode with the far greater performance level and associated higher performance ratios of the full power mode of this new storage technology as outlined earlier.

This proprietary new data storage technology is the subject of a pending patent application in the United States Patent and Trademark Office filed on October 5, 2007, with corresponding foreign applications to follow.

This Executive Summary has outlined what this new memory chip architecture represents in terms of what it can do without divulging how. Any electrical engineer or computer scientist on behalf of an interested party may certainly conference with the lead inventor of this new storage technology, Joseph Ashwood, for full disclosure of all matters regarding the construct and resulting breakthrough nature of this invention upon that party’s signing of a one page NDA (available upon request).

Executive Team:

JoAnne Leff is the founder and director of J. L. Associates, the company granted exclusive marketing rights by the inventors to sell or license this new data storage technology. She has over thirty years experience in new business development and sales support services, and is highly regarded for her national and global deal driving skills, marketing strategies and sales initiatives. She is an accomplished author and public speaker. JoAnne received a B.S. from Boston University and attended NY University for postgraduate work.

Joseph Ashwood is the lead inventor of the new storage technology at issue, and currently works as an Independent Global Cryptanalyst, Security Research Analyst and Design Consultant. He received a B.S. in Computer Engineering and Computer Science from the University of Southern California in 1999. Worked for Starbase in Irvine, CA as a Software Engineer Intern in 1999, and as Lead Cryptanalyst for Arcot Systems in Santa Clara, CA from 2000- 2001. Joseph has vast knowledge and experience in algorithm development, cryptographic security, the design and construction of tamper-evident audit logs, threat model maintenance, examination, design and redesign of computer security systems, has performed research on breaking the Java Virtual Machine, led development of replacement protocol for Kerberos computer security protocol, where he performed cryptanalytic verification, was instrumental in the creation of BITS standards, and contracted with senior business executives to build strong, easily managed security into their business processes. Special interests include all aspects of cryptography, industrial design (works of Lovegrove and Colani), electrostatic loudspeaker design and ending pandemics (GPHIN and INSTEDD).

Glenn T. Henneberger is a Partner in the law firm of Hoffmann & Baron in Syosset, New York and the Patent Attorney who prepared and filed the Patent Application dated October 5, 2007 on the storage technology at issue. He received a B.E. in Electrical Engineering from SUNY Maritime College in 1986 and a J.D. from St. John's University School of Law in 1991. Admitted to practice in the state court of Connecticut in 1991, the state and federal courts of New York in 1992 and the United States Court of Appeals for the Federal Circuit and the Supreme Court of the United States in 1995. Glenn is registered to practice before the United States Patent and Trademark Office. He worked as an Electrical Engineer for the Long Island Lighting Company from 1986-1991. Fields of technology include analog and digital circuitry, power systems, mechanical and electromechanical systems, computer hardware and software, medical and dental devices, lasers and optics. Experience includes domestic and foreign patent and trademark prosecution, copyrights, licensing of intellectual property and related litigation.

Contact Information:

JoAnne Leff, Marketing & Managing Director, J. L. Associates, 56 West 84th Street, Ground Floor Suite, New York, New York 10024 - (212) 874-2835 - jo-anne1@ix.netcom.com

Attachment A:

Attachment - A '); document.close(); }

EE Times:
Memory goes multicore

R. Colin Johnson
(01/14/2008 12:20 PM EST)
URL: http://www.eetimes.com/showArticle.jhtml?articleID=205604434

PORTLAND, Ore. — In the 21st century, instead of depending on continually shrinking design rules, microprocessor makers are harnessing multiple cores for parallel execution. Memory chip architectures, however, have not kept up, according to a cryptographer who claims to have created a memory chip architecture for the 21st century—one that matches multicore microprocessors with parallel, concurrent access to multiple memory chips.

"My design borrows extensively from today's modern multicore CPUs," said Joseph Ashwood, an independent security cryptanalyst and design consultant residing in Gilroy, Calif. Ashwood was lead cryptanalyst for Arcot Systems in Santa Clara, Calif., before going independent in 2001. "As far as concurrency goes, my memory architecture shares some features with Fibre Channel."

According to Ashwood, his architecture provides parallel access to bit cells on memory chips, breaking the serial bottleneck that is strangling nonvolatile storage media like flash, with an architecture that can be applied to any memory chip bit cell. The Ashwood memory architecture works by integrating smart controller circuitry next to the memory array on a single chip, providing parallel access to the array for hundreds of concurrent processes, thereby increasing throughput and lowering average access time.

"We have a new way of assembling the memory, with a few new elements I was led to by my experience with cryptography. I am basically applying very deep cryptographic techniques to memory architecture, resulting in a unique new design that is very fast and compact. Bringing in these new elements enables a lot of good things, especially concurrency, permitting hundreds of simultaneous memory operations," said Ashwood.

"Compared to DDR, for instance, my architecture goes inside the chip and reorganizes how the bit cells are accessed, thereby utilizing them much more efficiently," he added. "Transfer rate is faster, too—for instance, right now, DDR-II for DRAM only goes up to 12 Gbytes per second, but our architecture can deliver 16 Gbytes per second when using flash memory and is compatible with PRAM or any other nonvolatile semiconductor memory cells."

Sound too good to be true? JoAnne Leff, founder of J.L. Associates (New York), thought the same thing when she was first approached by Ashwood to represent him in licensing the technology. So she sent the design over to Carnegie Mellon University for confirmation.

"We were skeptical, of course, but Carnegie Mellon confirmed for us that the Ashwood memory architecture really is a breakthrough in memory design," said Leff. "Now we want to license it to all major players involved in the applications of this technology, not only to improve the performance of individual memory chips, but also to give users fast, parallel access to solid-state drives."

Carnegie Mellon's evaluation for J.L. Associates claims that solid-state drives using nonvolatile memory chips is an especially good application, and that the Ashwood memory architecture could rejuvenate the nonvolatile memory markets, such as flash, by improving their performance today and tomorrow, since scaling to larger capacities also increases concurrency.

"This new technology enables parallel data storage and access on a single nonvolatile memory chip. The scalability created by this technology provides superior speed in accessing and storing data with higher storage capacity at a single chip level. With on-chip power management, the technology is truly enabling for applications that require on-chip high-speed data transfer for various high-capacity, nonvolatile memory devices," said the Carnegie Mellon evaluation. "It has been predicted by many people, such as Gordon Bell, that by 2015 personal devices such as PDAs and cell phones will need to have a nonvolatile storage capacity of at least 1 terabyte. This memory technology invention provides a solution to meet that need."

Ashwood, however, does admit to two downsides to his memory architecture. First, it is still just a paper design. He plans to work with licensees to implement his design on their memory arrays, but so far only a software simulation has been completed.

"I have fully developed the memory chip architecture, and I have run a software simulation to verify that it works, but so far I have not done a design at the electrical signal level—that kind of detail is dependent on who ends up licensing it," he said.

The second downside is that the parallel access overhead of the Ashwood memory architecture slightly slows down memory access times to individual memory cells—a disadvantage that is offset by its many parallel access channels, Ashwood said.

"For instance, if a NAND flash chip has an access time of 20 to 50 nanoseconds today, adding my architecture would increase that access time to 50 to 70 nanoseconds," he said. "But remember, during that time, 100 or more other memory retrieval operations could be in progress concurrently, yielding an effective access time of just a few nanoseconds per retrieval."

Late last year Ashwood filed a patent on his memory architecture, but because chip makers could implement it before the patent is grated, he is choosing to keep most of the architecture secret until the patent is granted next year

"This architecture is so easy to implement—a chip maker could roll out a working prototype in as little as three months," said Ashwood.

Ashwood, however, has disclosed the main outlines of its functions—reorganizing the memory hierarchy for parallel access to a chip's data—as well as described its features and made performance comparisons with both DRAM and hard disks.

"Unlike traditional memory architectures that degrade in performance as more bit cells are added to an array, our memory architecture's performance increases each time you add cells," said Ashwood. "For instance, because of the way our architecture scales, if you double the capacity of our memory chip, it also becomes twice as fast as before."

Overhead is low, too, adding only about 3 percent to the die area of a memory chip, according to Ashwood.

"Current flash cells are already extremely dense—they should be able to fit a terabyte in less than a cubic inch," said Ashwood. "The problem is that their yields would fall to 30 percent and the speed to just 32 million bytes per second. Utilizing my technology with the same flash cells allows a yield in the upper 90 percent [range] and a speed of 16 billion bytes per second."

When using the Ashwood memory architecture with multiple flash chips configured as a solid-state disk (SSD), instead of adding 3 percent, each memory chip's die area could actually be smaller than it is today, because the access circuitry to the SSD would be common to all the memory chips on the drive, he said.

Using his memory architecture will also increase the lifetime of a drive, according to Ashwood. Flash cells can only endure about 100,000 cycles before they burn out. By offering greater flexibility in the page reassignment, he said, the Ashwood memory architecture can increase the lifetime of a drive by about 500 times.

Conclusion: In sum, it would seem that this new memory chip architecture has the capability to open the door to a completely new level of consumer device and networked storage that simply does not exist now.
Views: 395
Domain: Electronics
Category: Semiconductors
SEMICONDUCTOR ANALYTICS
JoAnne Leff
21 January, 2008