Linley Newsletter: Nov 1, 2018

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Linley Newsletter

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Issue #624

November 1, 2018


Independent Analysis of Microprocessors and the Semiconductor Industry

Editor: Tom R. Halfhill

Contributors: Bob Wheeler, David Kanter


In This Issue:

- Eta Compute MCU Puts AI in IoT

- Tachyum Tries for Hyperscale Servers


Eta Compute MCU Puts AI in IoT

By Bob Wheeler

Riding the AI-in-IoT wave, Eta Compute has developed an SoC that combines an MCU with a DSP for machine learning. The ultra-low-power Tensai chip is well suited to battery-operated systems, including those that require continuous (always-on) processing. The startup completes its solution with optimized neural-network software for machine learning. It expects Tensai to enter production early next year.

Tensai starts as a hyper-efficient microcontroller built around Eta's asynchronous CPU core and low-power analog blocks. The startup previously disclosed its Cortex-M3 CPU, which it also licenses as a 55nm hard macro. For machine learning, it adds a CoolFlux DSP16 core licensed from NXP. It uses the DSP's dual 16x16 MACs to implement convolutional neural networks (CNNs) as well as spiking neural networks (SNNs). Tensai has common MCU features such as embedded flash memory, analog I/Os, and a power-management unit.

By crunching data at its source, Tensai can dramatically reduce communications requirements for IoT devices. Applications include cameras that detect and track objects, smart speakers with wake-word detection, and industrial sensors that detect anomalies without extensive offline training. Eta isn't alone in addressing edge AI, but it's the first to offer an Arm-based MCU with a machine-learning engine. Its holistic approach should appeal to IoT developers lacking AI expertise.

Microprocessor Report subscribers can access the full article:

http://www.linleygroup.com/mpr/article.php?id=12050

Tachyum Tries for Hyperscale Servers

By David Kanter

Tachyum is developing a 64-core server processor in 7nm technology for hyperscale data centers, targeting tapeout late next year. The design implements a VLIW instruction set with custom vector and matrix-multiplication instructions as well as a custom fabric.

The Prodigy core is a four-bundle eight-wide design with a short 9-stage integer pipeline and 14-stage floating-point pipeline. It packs four integer units, two vector multiply-accumulate units that are 512 bits wide, a vector permute unit, and three load/store pipelines. It can sustain 192 bytes per clock from the 16KB L1 data cache, which is backed by a 512KB L2 cache. Using 8x8 and 4x4 matrix-multiplication instructions, the core can deliver 1,024 and 512 operations per clock, respectively, for machine learning and HPC.

Although the pipeline is largely in order, the microarchitecture has some limited reordering capabilities around load misses; Tachyum claims they'll provide some benefits of out-of-order execution. The startup claims Prodigy should be more efficient than out-of-order designs while delivering similar or better performance.

The Tachyum server processor comprises a mesh fabric that connects 64 compute tiles, including a Prodigy core and 512KB of configurable L3 cache. The L3 operates as either a private victim cache for better locality or up to a 32MB slice of distributed shared L3 cache. For external memory, the processor has eight DDR4/5 channels. The 72 multimode-serdes lanes are typically configured as 64 PCIe 5.0 lanes and two 400G Ethernet links.

Tachyum claims the power-efficient Prodigy core and a simple mesh fabric will reach 4.0GHz in 7nm at 0.825V for a total chip power of 180W, even when the vector units are active. Given that the chip has yet to tape out and has specifications similar to those of other processors, these claims may prove optimistic.

Microprocessor Report subscribers can access the full article:

http://www.linleygroup.com/mpr/article.php?id=12052

About Linley Newsletter

Linley Newsletter is a free electronic newsletter that reports and analyzes advances in microprocessors, networking chips, and mobile-communications chips. It is published by The Linley Group. To subscribe, please visit:

http://www.linleygroup.com/newsletters/newsletter_subscribe.php

Domain: Electronics
Category: Semiconductors
SEMICONDUCTOR ANALYTICS

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