Linley Newsletter: August 16, 2018

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Issue #613

August 16, 2018

Independent Analysis of Microprocessors and the Semiconductor Industry

Editor: Tom R. Halfhill

Contributors: Linley Gwennap, Mike Demler, Bob Wheeler

In This Issue:

- Intel to Offer Structured ASICs

- Microchip Debuts Dual-Core DSC

- IBM Trains in Analog to Save AI Power

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Intel to Offer Structured ASICs

By Linley Gwennap

Intel's pending acquisition of eASIC shines a light on structured ASICs, a niche technology in the vast ASIC market. Intel sees the move as complementary to both its large FPGA business (formerly Altera) and its custom-ASIC business (formerly part of LSI). The company plans to invest in the new business to move its structured ASICs to the next process node and add new hard cores to the platform. It declined to reveal how much it paid for eASIC, saying the price is immaterial to earnings.

Structured ASICs are similar to FPGAs in providing a pool of logic cells, memory cells, and I/O drivers that can be connected to create a variety of designs. Whereas customers configure an FPGA dynamically at run time, they configure a structured ASIC by modifying a single layer of the chip design. This approach eliminates much of the overhead of an FPGA, locking in cost and power savings. Although customers must create the structured-ASIC design before manufacturing, the design process is much simpler than for a custom ASIC. Thus, the structured ASIC provides an intermediate step between an FPGA and a custom ASIC.

Structured ASICs (also called gate-array ASICs) have existed for decades. Several ASIC vendors, such as Fujitsu, LSI Logic, and NEC, once offered them, but all exited the market by 2007. Altera used a similar technology as part of its FPGA-conversion program called HardCopy, but it eventually discontinued this program as customer interest dwindled. Toshiba continues to offer a similar customizable product it calls FFSA, with but modest success. The other vendor that has persevered with this technology is eASIC. We estimate the privately held company's annual revenue at less than $100 million, representing considerably less than 1% of the total ASIC market.

Microprocessor Report subscribers can access the full article:

Microchip Debuts Dual-Core DSC

By Tom R. Halfhill

Microchip's new dsPIC33CH is an unusually capable 16-bit digital signal controller (DSC) that combines the functions of a microcontroller and DSP. Actually a family of more than 50 chips, the 33CH integrates two PIC CPUs in a master-slave configuration that enables the slave to continue operating even if the master reboots to recover from a fault.

The new family targets embedded systems that need real-time control and signal processing. Examples include electric-motor controllers, server power supplies, automotive sensors, and small drones. Some models are certified for automotive temperatures (-40ºC to +125ºC), so they're suited to under-the-hood applications, such as fan controllers and pumps. Although the chips lack duplicate lockstep cores, the slave's ability to operate independently of the master provides greater functional safety than a single-core chip.

Both cores are proprietary 16-bit PIC CPUs with signal-processing extensions. The master runs at 180MHz and the slave at 200MHz. Microchip says they deliver about 1.2 EEMBC CoreMarks per megahertz -- about half the performance of Arm's Cortex-M0+. Many 32-bit MCUs don't reach such high clock speeds, however, so these humble 16-bit cores can outrun them. Microchip's own SAM L10/L11 MCUs, which employ the newer Cortex-M23 CPU, peak at only 32MHz.

The 33CH family is available now in eight different packages that have 28 to 80 pins and measure 5mm to 12mm square. List prices range from about $3.00 to $4.30 for 1,000-unit volumes. A general-purpose development board costs only $35, and a motor-control module is $25. The chips are programmable in C using Microchip's GCC-derived compiler and code libraries.

Microprocessor Report subscribers can access the full article:

IBM Trains in Analog to Save AI Power

By Mike Demler

Neural networks consume most of their power moving data to and from memory. To ameliorate this problem, researchers at IBM and other companies are developing methods for performing some calculations directly in memory. IBM is using phase-change memory (PCM), a nonvolatile storage mechanism that enables high-precision analog multiplication. It employs storage cells composed of materials that change conductance by as much as four orders of magnitude when heated over a large temperature range.

At this stage of its PCM research, IBM's primary goal is to demonstrate that the technology can match the accuracy of neural networks trained using popular digital methods, while consuming less power. Although the company's comparison with a TensorFlow model was completely in software, its test results accomplished that goal. The PCM-based network matched TensorFlow's accuracy on the MNIST database of handwritten characters and the CIFAR-10 image data set, and it was within 1% on CIFAR-100.

Nevertheless, performance is critical to neural-network training as well, since huge data sets can take hours to process. We expect the PCM technique is more likely to succeed in embedded applications. The nonvolatile memories are also ideal for fixed-function inference engines, since they retain their network calibration even after losing power. To take advantage of the area and power efficiencies of its design, IBM should focus on low-power IoT clients and similar applications, which could benefit from retraining in the field using newly acquired sensor data.

Microprocessor Report subscribers can access the full article:

About Linley Newsletter

Linley Newsletter is a free electronic newsletter that reports and analyzes advances in microprocessors, networking chips, and mobile-communications chips. It is published by The Linley Group. To subscribe, please visit:

Domain: Electronics
Category: Semiconductors

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