Linley Newsletter: October 4, 2018

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Issue #620

October 4, 2018

Independent Analysis of Microprocessors and the Semiconductor Industry

Editor: Tom R. Halfhill

Contributors: Linley Gwennap, Mike Demler, Bob Wheeler

In This Issue:

- NRAM Brings Nanotubes to Silicon

- Marvell Reveals Post-Cavium Roadmap

- NetSpeed Disappears Into Intel

NRAM Brings Nanotubes to Silicon

By David Kanter

Nantero is pioneering the use of carbon nanotubes (CNT) in a silicon process to create NRAM, a new type of resistive nonvolatile memory. NRAM should offer DRAM-like performance and density with nearly unlimited endurance and retention. The company licenses this technology to other companies that will manufacture and sell NRAM products. The first such products could reach production in 2020.

NRAM formation employs CMOS-compatible technology steps in a chip's interconnect layer and is vertically stackable. NRAM cells can operate in both single-layer and 3D multilayer configurations to emphasize density or performance. The properties of CNT naturally maintain the cell's resistance in either a high or low state that a chip can sense during a read. Writing a cell is more complicated and requires a higher (but still logic-friendly) voltage to change the CNT positioning.

Nantero has spent 17 years developing the CMOS-compatible CNT materials, the CNT-deposition process, and the methods for integrating that process into CMOS flows as well as for characterizing many of NRAM's unique properties. Among these properties are extreme write endurance, near immunity to soft errors, high temperature tolerances, low-power operation, and DRAM-like latencies. Many the NRAM properties have been verified on test chips, including a 140nm 4Mb design.

The company's next step is to prove that CNT manufacturing flows can yield at high volume by productizing a 28nm 16Gb memory that recently taped out and by integrating that memory into a standard DDR4 DIMM.

Microprocessor Report subscribers can access the full article:

Marvell Reveals Post-Cavium Roadmap

By Bob Wheeler

As Marvell works to integrate its Cavium acquisition, it's paring unneeded and overlapping product lines. The changes affect both Cavium and Marvell roadmaps despite the acquirer's earlier claim that roadmaps would be unaffected. Unsurprisingly, the changes eliminate overlapping product lines in embedded processors and Ethernet switching -- we observed last year that Marvell would have to revisit the roadmaps for these lines. The acquirer also divested Cavium's Monta Vista software, a small legacy business.

In embedded processing, the company consolidated its roadmap around Cavium's Octeon line, which in 2017 generated about 2.5x the revenue of Marvell's Armada line. It will continue to support Armada customers, but its roadmap will focus on Octeon TX. Also, Marvell says it'll continue Cavium's ThunderX2 line of Arm server processors, which are starting to win customer designs. In Ethernet switching, the company chose to focus on its established Prestera line and halt development of the programmable Xpliant line from Cavium. It will support existing Xpliant customers but has already combined the Cavium and Marvell switch-development teams.

Cavium's revenue contribution for the first quarter after the acquisition was well below expectations, as was its revenue before the acquisition closing. On the plus side, Marvell now expects $200 million in annual cost reductions ("synergies") versus a prior range of $150 million to $175 million. At the same time, it's maintaining its prior revenue-growth target of 6-8%, so the cuts don't represent a strategic shift. Having completed the integration of Cavium, Marvell can now focus on product execution in its newly pruned roadmaps.

Microprocessor Report subscribers can access the full article:

NetSpeed Disappears Into Intel

By Linley Gwennap

Network-on-a-chip (NoC) vendor NetSpeed Systems is now part of Intel, giving it a good exit but leaving its customers without a roadmap. The deal gives the x86 giant full access to and control of NetSpeed's tools, which simplify development of large processors and SoCs by automating the design of the on-chip interconnect, or NoC. We expect Intel will use these tools to engineer its next-generation PC and server processors. It will continue to support existing NetSpeed customers, but we don't expect it to offer them any new products or major revisions to the NoC technology.

NetSpeed has developed several generations of its NoC intellectual property (IP), called Gemini. The company raised $13 million, mainly from Walden Ventures and Intel Capital. Lip-Bu Tan, Walden's chairman, is also CEO of Cadence (and chairman of NetSpeed's board), and NetSpeed operated for years out of a Cadence building, leading to speculation that the EDA-tools vendor would ultimately acquire NetSpeed. Instead, the startup went to Intel. The chip giant was already a customer, using the NetSpeed tools to develop its latest FPGAs. Jim Keller, who recently joined Intel, led the acquisition. The team is now part of Intel's massive Silicon Engineering Group, which Keller manages. Former CEO Mitra continues to lead the team as an Intel vice president.

Unfortunately, NetSpeed's other customers are left in the lurch. Intel will honor all existing contracts for product delivery and support, but it's unlikely to extend these contracts or sign new ones. Once these customers finish their current designs, they'll probably turn to other NoC vendors. The biggest beneficiary will likely be Arteris, which has a similar range of products. Sonics also offers NoC IP. The NetSpeed acquisition strengthens Intel's design capabilities while consolidating the small but growing NoC market.

Microprocessor Report subscribers can access the full article:

About Linley Newsletter

Linley Newsletter is a free electronic newsletter that reports and analyzes advances in microprocessors, networking chips, and mobile-communications chips. It is published by The Linley Group. To subscribe, please visit:

Domain: Electronics
Category: Semiconductors

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