Leadless Flip Chip PLGA For Networking Applications

Leadless Flip Chip PLGA For Networking Applications

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Description: Initial SMT assembly trials with 1:1 stencil and only minimal (<10 mm) solder on LGA pads resulted in some outer row solder joint opens. Decision made to provide 100 mm pre-applied solder bumps on the package LGA pads.

 
Author: Andrew Mawer, Paul Galles Steve Safai, Trent Uehling  | Visits: 311 | Page Views: 566
Domain:  High Tech Category: Semiconductors 
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Contents:
LEADLESS FLIP CHIP PLGA FOR
NETWORKING APPLICATIONS
Andrew Mawer1, Paul Galles Steve Safai
and Trent Uehling
NXP Semiconductors N.V.
1Email:

andrew.mawer@nxp.com
Phone: +1-512-895-7925

Outline


Motivation



Component Details



Reflow Warpage
PCB Pad Designs





Solder Paste Stencil Design
Solder Reflow Profile



X-Ray Inspection



Board-Level Reliability Testing



Conclusions / Future Work
Acknowledgements / Questions





Motivation for Packaging Miniaturization


Traditional packaging for networking processors has been FC
PBGA with relatively large body sizes ranging from 17 to 45 mm at
pitches of 0.8 to 1.27 mm (examples below)



Newer IoT gateway and other miniaturized, cost sensitive
applications require smaller form factor packaging

Source: http://cache.nxp.com/files/32bit/doc/package_info/FC-PBGAPRES.pdf?fsrch=1&sr=2&pageNum=1

Motivation for Packaging Miniaturization


9.6 x 9.6 x 0.805 mm Flip Chip Plastic Land Grid Array (FC PLGA)
developed for new 64 bit ARM based network processor



Shown below with 1295 pin, 37.5 x 37.5 mm FC PBGA high-end
network processor for comparison

211, 9.6 x 9.6 mm
FC PLGA

1295, 37.5 x 37.5 mm FC PBGA

211 FC PLGA Details


211 molded FC PLGA



0.805 mm unmounted pkg
thickness with LGA bumps

Flip Chip Die

Pb-Free Bumps

9.6 x 9.6 mm body size



Mold Compound



Three metal layer, 0.18 mm
thick coreless substrate



0.5 mm pitch perimeter 0.22
x 0.26 mm package LGA
pads



0.8 mm pitch center and
corner 0.45 x 0.45 mm
package LGA pads

Package Cross-Section View

SnAgCu bumped LGA pads



Substrate

Package Bottom View

211 FC PLGA Bottomside Package Drawing


Two outer rows of 0.5
mm pitch pads



9 x 9 inner array of
larger mainly power /
ground pads at 0.8 mm
pitch that are rotated 45°
to enable larger
diameter interstitial vias



6.6 × 4.9 mm die outline
shown in blue

211 FC PLGA Component Details


Detailed list of package attributes:
Item
Package Body Size
Package Thickness

Value
9.6 × 9.6 mm
0.805 mm

With Solder Bumps

Joint Stand-Off Height after Board Mount

150 – 200 mm

Pad / Paste Dependent

Total LGA Pads
Package LGA Pad Type
LGA Pad Bump Heights

Total Perim LGA Pads
Total Center LGA Pads
Total Corner LGA Pads
Perim LGA Pad Pitch
Perim LGA Pad Size
Center LGA Pitch
Center and Corner LGA Pad Size
Substrate Cu Layers
Substrate Thickness
Mold Cap Thickness
Product Power

Comment

211
Soldermask Defined
(SMD)
100 +/- 50 mm

SnAgCu Solder Bumps

126
81
4
0.5 mm
0.22 × 0.26 mm
0.8 mm
0.45 × 0.45 mm
3
0.18 mm
0.53 mm
~1 W

Two Rows
9 × 9 Array

Coreless
Including Soldermask
Typical

211 FC PLGA Flip Chip Details


Package Pb-free flip chip bump overview
20 mm

Flip Chip Die

Mold
Compound

Pb-Free Bump

Soldermask

Substrate Bump Pad
Substrate

211 FC PLGA SnAgCu LGA Bumps


Nominal 100 mm tall SnAgCu (SAC305) bumps on the LGA pads on
bottomside of the substrate



Originally envisioned as a pure LGA, but solder added later for additional SMT
assembly robustness



Solder paste printing process used in component assembly

Side View Showing SAC Bumps

Test Mark

Cross-Section of Typical SAC Bump

Package Warpage vs Reflow


For LGA-like packages especially, excessive warpage at
reflow can lead to SMT assembly issues



Package bottomside warpage was measured with bumps
removed during a reflow up to 260°C peak temperature
mm

Typical Room Temp Warpage of 34 mm

Typical 260C Warpage of 23 mm

Package Warpage vs Reflow




Five parts were measured using the TherMoiré technique with
all warpages measured at