3D-Integrated Circuit Technology

3D-Integrated Circuit Technology

Loading
Loading Social Plug-ins...
Language: English
Save to myLibrary Download PDF
Go to Page # Page of 24

Description: Topics discussed include Classification of 3D Stacking Technology, Need to Develop 3D-Integration Technology, Fields of Application for Dream Chips (3D Stacked SiP), Development of Functionally Innovative 3D-Integrated Circuit (Dream Chip) Technology, High-Density 3D-Integration Technology for Multifunctional Devices, R&D on High Speed Electrical Circuitry Simulation Engine, R&D on Signal Integrity (SI) Technology and Power Integrity (PI) Technology, and Chip Test Technology.

 
Author: Morihiro Kada (Fellow) | Visits: 2434 | Page Views: 2857
Domain:  High Tech Category: Semiconductors 
Upload Date:
Short URL: https://www.wesrch.com/electronics/pdfEL1SE1000OLDR
Loading
Loading...



px *        px *

* Default width and height in pixels. Change it to your required dimensions.

 
Contents:
Development of Functionally Innovative 3D-Integrated Circuit (Dream Chip) Technology

Association of Super-Advanced Electronics Technologies Morihiro Kada
July, 2009

1

�2009 Association of Super-Advanced Electronics Technologies

Over View of 3D-Integrated Circuit Technology

July, 2009

2

�2009 Association of Super-Advanced Electronics Technologies

Classification of 3D Stacking Technology
Source: Sharp, Tohoku University

3D Chip Stacking Technology Chip stack
WB FC Package stack WB PoP
TSV chip stack


TSV: Through Si Via

Wireless chip stack



Used with chip stacking WB type 1998

FC type 2006

2002
Digital cameras, mobile phones
3

2010 and later ~

Mobile phones, digital cameras, image processing devices

High-end devices High-speed image processing devices

??

July, 2009

�2009 Association of Super-Advanced Electronics Technologies

Need to Develop 3D-Integration Technology
Through Si Via (TSV) are effective for 3D-integration of semiconductor chips
-Connecting distance is about 1/1,000 -Enables ultra-wide buses

Enables 3D-integration of CMOS semiconductor devices with other functional devices

-High-speed large-capacity transmission -Low power consumption

Unprecedented multifunctional devices-heterogeneous integration

Conceptual diagram of next-generation 3D stacked SiP Conceptual diagram of next-generation 3D stacked SiP
Design Environment Technology Chip/SiP/PCB linked design tools Electric/Thermal/Mechanical Coordinated Design


Device Demonstration

A DR

M

FLASH/SRAM


I/O

RF DSP

(Known Good Die) Chip Test Technology KGD(Known Good Die)

Interposer





3D-Integration Basic Technology (Interposer Technology, Cooling and Stacking/Bonding Technology etc.)

July, 2009

4

�2009 Association of Super-Advanced Electronics Technologies

Fields of Application for Dream Chips (3D Stacked SiP)

Cutting Edge Healthcare/Bio
Capsule endoscopes, artificial organs, behavior management monitors, smart shirts for medical care etc.

Futuristic Robots
AI robots, neuro-computers, household robots

Laptop Super Computers

Advanced Futuristic Consumer Electronics
Simultaneous translation capability (enabling conversation with people throughout the world) TV-equipped mobile phones Wall-mounted TVs enabling viewing of foreign films in Japanese Ultra high-speed, high-precision cameras

Chip the size of a sugar cube, with the function of a PC, mobile phone or TV (3mm~1cm)

Laptop Super Computers

Combination of MEMS, analog, logic and memory chips etc.

Ultra HighPerformance Games
High-performance next-generation game machines

Auto-Pilot for Cars Human Interfaces
Speech recognition Virtual keyboard Cars equipped with collision prevention, dozing detection, automatic travel to destination and automatic driving features

Ubiquitous Computing
Wearable computers, sensor networks

July, 2009

5

�2009 Association of Super-Advanced Electronics Technologies

Development of Functionally Innovative 3D-Integrated Circuit (Dream Chip) Technology

July, 2009

6

�2009 Association of Super-Advanced Electronics Technologies

NEDO Project for "Development of Functionally Innovative 3D-Integrated Circuit (Dream Chip) Technology"

~FY2009
Entrustment

Source

NEDO
3)Threedimensional Reconfigurable Device Technology

New Energy and Industrial Technology Development Organization(NEDO)

1) High-density Three-dimensional Integration Technology for Multifunctional devices

2)Three-dimensional Integrated RF Device Technology for Multiband Communication Systems
Fujitsu Tokyo Institute of Tech.

ASET


Flash/SRAM DRAM CPU Interface/Power supply DSP etc DSP etc
FPGA

3D wiring

MEMS (Tunable MEMS Circuits)
MEMS Controller/ Power supply RF-CMOS RF-CMOS Transceiver/ LSI

Switch Capacitor Inductor

3D FPGA

Base Band LSI

July, 2009

7

�2009 Association of Super-Advanced Electronics Technologies

Research Overview
Project name: Project under NEDO entrustment in FY2008 "Development of Functionally Innovative 3D-Integrated Circuit (Dream Chip) Technology" -High-Density 3D-Integration Technology for Multifunctional Devices -Three-dimensional Reconfigurable Device Technology Project term: FY2008 ~ FY2012 (5 years) Research Fund: FY2008 850 million yen FY2009 1.5+ billion yen
July, 2009

Project Concept

2012 Main research 2008 (Dream Chip) Preliminary research 2007 Technical 2006 Survey research

8

�2009 Association of Super-Advanced Electronics Technologies

Member Companies of the Project and its Organizations ~FY2009
ASET (Private sector consortium: 19 firms) 75people
Joint research, 45 people Research results going back to basic science

Device manufacturers

-NEC Electronics -Elpida Memory -Toshiba -Renesas Technology -Rohm -NEC -Sharp -nac Image Technology -IBM Japan -Panasonic -Hitachi
-Advantest -Ibiden -Zycube -Shinko Electric -Dai Nippon Printing -Toppan Printing -Tokyo Electron -Yamaichi Electronics

Universities
-Kyoto University -Shizuoka University -University of Tokyo -Tohoku University -Toyama Prefectural University -Shibaura Institute of Technology -Meisei University

Electronic equipment manufacturers

Joint research

Research institution.

Materials/ System Manufacturers etc.

AIST
The National Institute of Advanced Industrial Science and Technology

July, 2009

9

�2009 Association of Super-Advanced Electronics Technologies

Research and Development Result in FY2008

Development of Functionally Innovative 3D-Integrated Circuit (Dream Chip) Technology

High-Density 3D-Integration Technology for Multifunctional Devices

July, 2009

10

�2009 Association of Super-Advanced Electronics Technologies

-A R&D on Design Environment Technology R&D Themes
1A1R&D on High Speed Electrical Circuitry Simulation Engine Develop Revolutionary Algorithm for Super Fast Calculation Develop New Simulator Based on the Developed Algorithm Develop the Interface for the Product Development 1A2R&D on High Speed Electromagnetic Field Simulation Engine Develop Revolutionary Algorithm enabling FDTD Method and further Speed Up Develop New Simulator Develop the Interface for the Product Development 1A3R&D on Integrating High Speed Electric Circuitry and Electromagnetic Field Simulation Engine 1A4Investigation of Integrating Thermal/Mechanical Simulator and Electrical Simulator
FDTDFinite Difference Time Domain

July, 2009

11

�2009 Association of Super-Advanced Electronics Technologies

-A R&D on Design Environment Technology
Board Configuration of Recent Digital Appliances
Board (PWB) A SiP Highspeed memory NAND SoC (Logic) A' Memory bus 200MHz1GHz High-speed memory (SDRAM)
High-speed serial

FY2008 R&D Results
NAND Flash High-Speed Memory SOC SiP substrate

Cross-section of SiP part (A-A')
TSV (Through Si Via)

Analog (~GHz) RF-IC

Board (PWB)

Digital (Low speed)

Digital (2.5Gbps)

(A1) R&D on High Speed Circuitry Simulation Engine (A2) R&D on High Speed Electromagnetic Field Simulation Engine

Circuit Equivalent to the System
Flow 1 File I/F

Electromagnetic Field Simulator
-Use combination of FDTD method and parallel computation Result: 120times increase in speed

Circuitry Simulator
- Develop new calculation algorithms - Use parallel computation Result: 240times increase in speed 1A3R&D on Integrating High Speed Electric Circuitry and Prospect increased precision by integrating electromagnetic field analysis and circuit analysis Electromagnetic Field Simulation Engine
July, 2009
Flow 2 Direct Integration

FDTDFinite Difference Time Domain

12

�2009 Association of Super-Advanced Electronics Technologies

- R&D on Interposer Technology
-Wide band, low impedance power supply circuitry -Multiple power supplies, highly efficient on chip distribution P/S circuitry -Interposer development for enbedded 3D integration SiP
VIN=3.3V Driver VOUT 1V,100mA Comp. Error amp. VREF

R&D Themes

1B1R&D on Signal IntegritySI and Power IntegrityPI Technology

Embedded in an interposer

Embedded LL 4�m (4m-thick Cu) L Embedded L 15�m (15m thick Cu) V =3.3V
IN

Capacitor enbeded interposer

VOUT=1.0V

On-chip L L linear Theoretical limit of regulators

Embedded in chip component

Thin-film capacitor integration

DC-DC converter circuit Simulated DC-DC converter efficiency High-precision simulation of interposer with embedded elements is difficult

ChipPKGBoard Integration P/S Design

1B2 R&D on Evaluation and Testing Technologies of passive enbedded Interposer
-Develop ultra low impedance precise measurement method -Develop high accuracy simulation and its measurement method for passive enbedded interposer -Develop standard testing method for the passive enbedded Interposer

Thin Film Cap. 1.2F (Meas.) Embedded Cap. 2.4F (Meas.) Thin Film Cap. 1.2F (Sim.) Embedded Cap. 2.4F (Sim.)

July, 2009

13

�2009 Association of Super-Advanced Electronics Technologies

- R&D on Interposer Technology

FY2008 R&D Results

1B1 R&D on Signal Integrity(SI) Technology and Power Integrity(PI) Technolog - Completed design evaluation for I/F chips (driver, serial-parallel conversion) - Completed design and prototyping of interposer for high-speed I/O driver
* Prototyping of surface mount, embedded component, Si interposer * Prediction of achieving 20Gbps SI by improving master design of simulation base

- Completed design and prototyping of power noise evaluation system using FPGA
Example of SI improvement by countering Z0 mismatch at via
Simulation

Power noise evaluation system

Example interposer for driver IC

20Gbps transmission impossible

FPGA
Driver chip mounting part

Simulation

20Gbps transmission possible

July, 2009

14

�2009 Association of Super-Advanced Electronics Technologies

- R&D on Chip Test Technology
2A1R&D on Contact and Contactless Coupling Probing Technology for the Wafer -More than 300K points Contact and Contactless Intereconnections for 300 Wafer -R&D on the Probe Card with Contactless Terminals(C ,L Coupling) -Develop High Speed Signal Terminal ( Chip Access =>15Gbps) -Speed-up of Contactless TerminalReceiving Circuitry 2A2R&D on Electrical P/S and Temperature Control Technologies for the Device under Test -Wafer Burn-in Test for Realizing KGD at -40Cdegree+125Cdegree -Develop P/S Method to the Wafer with kA Current -Positioning and Cooling Method on the Probe with Large Current P/S -Develop Temperature Control and Cooling Method of 10kW Class Heat Generation 2A3Research on Connecting Technology between Probing Portion and Test System -Connecting Technology Enabling High Speed, High Density, Mating Tolerance, Insertion/Extraction Force Relief. -Develop Contactless(C/L- coupling) Terminal with High Density Compact Connector -Create Prototype Chip for C/L-coupling and Evaluate -Develop the Connector for Large Current P/S

R&D Themes

Conceptual drawing of probe card for next generation wafer testing (example
non contact probe

Receiver circuit Transmitter
Parasitic capacity

tester chip

tested chip

Conceptual drawing of test circuitry(receiving portion ) with non contact probe

Power I/O Supply

Signal
non contact ZIF(Zero Insertion Force) signal connector transceiver IC portion of probe card

Power Supply Connector (specified for big current)

wafer

Connecting structure image between probe card and test head

July, 2009

15

�2009 Association of Super-Advanced Electronics Technologies

- R&D on Chip Test Technology

FY2008 R&D Results

Wafer Probe Concept
Specifications: 300,000 electrodes 15Gbps 5kA,10kW/Wafer

(2A1: Non-contact probing)


(2A3: Non-contact connector)

data(Tx) data(Tx) data(Rx,150um2) data(Rx,80um2)

(Measurement situation)

data(Rx,100um2)

(Measurement situation)

data(Rx)

(Transmission waveforms )
X X direction
80 70 60 50 40 30 20 10 0 0 100 200 300 400 500 600 700 800 900 1000 [Mbps] Transmission speed [Mbps] 80 70 60 50 40 30 20 10 0 0 100 200 300 400 500 600 700 800 900 1000 [Mbps] Transmission speed [Mbps]

(Transmission waveforms )

Y Y direction

[um]

[um]

(Shape prototype appearance)
-Confirmed basic operation of C coupled receiving circuit -Confirmed transmission performance exceeding 500Mbps

(Permissible position accuracy ) In case of

data(Rx,80um2)

-Confirmed basic operation of C coupled recieving circuit -Confirmed 1Gbps transmission performance July, 2009

16

�2009 Association of Super-Advanced Electronics Technologies

- R&D on Cooling and Stacking/Bonding Technology
(2B1)-1 R&D on Thermal Evaluation and Cooling Technologies Design Technology Optimization for High thermal Transfer of Chip stacking Structure Develop High Accuracy Thermal Characteristics Evaluation Technology for Micro Structure and Ultra Thin wafer bonding Structure Develop Micro Structure -High Accuracy Simulation Technology Develop Filling Material for High Thermal Transfer Space Propose a Optimum Thermal Design Criteria for the Integrated Structure Develop Small and High Efficiency Cooling Structure (2B1)-2 R&D on the Evaluation and Analysis Technologies for the Stacking/ Bonding Highly Reliable Bonding Technology between Chips of Multiple Micro Bondings (Bump Diameter to be less than 5m and Number of Bumps to be more than 10,000) Non Destructive Inspection and Evaluation/ Analysis Technologies for Submicron Failures Propose an Optimum Design Criteria for High Yield Integration Process/Structure/Material
July, 2009 Modeling

R&D Themes

Compound (Bonding & Air) Individual Bonding & Air Thermal Thermal Resistance Resistance
9m (50m thick) (50m thick) 100m 200m

Si

200m














200m

100m 200m



Simulation(Temperature distribution)

17

�2009 Association of Super-Advanced Electronics Technologies

- R&D on Cooling and Stacking/Bonding Technology
(2B1)-1 R&D on Thermal Evaluation and Cooling Technology

FY2008 R&D Results

Increase in heat conduction of chip stacked structure - Completion of thermal TEG design and mask fabrication for high-precision evaluation of thermal characteristics - Development of microstructure/high-precision simulation technology Set-up of simulation tools, measuring equipment Will examine miniature, high-efficiency cooling structure

9x9mm 40WMax./chip
Temperature sensor (Diode) Wiring layer

Heating side Test piece

Balance arm

Simulation tool set-up Completed verification of 1 column model Measurement module To model
Weight

Hotspot heater (Diffusion layer)

Cooling side Copper rod

1m Set-up equipment for measuring heat conduction Hot of microstructure spot (element) SiCOH SiN1m

Chip Chip Chip Chip

Cu 20- 50m
Wiring layer 1m 5m

Will compare of simulation and demonstration Brush up simulation model and parameters High-precision simulation

Measurement module

July, 2009

18

�2009 Association of Super-Advanced Electronics Technologies

- R&D on Thin Wafer Technology

R&D Themes

(2C1) R&D of Evaluation and Analysis Technologies for Thin Wafer
Develop Ultra Thin Chip Process Technology of 300mm Wafer, 10�1m Thickness
Realization of Highly Reliable Device or Process Method with Least Characteristic Deviation Develop Backside Thinning Process Offering Gettering Capability with Good Mechanical Strength.
DZ layer BMD layer Over 100m
Wafer Cross Sectional Image

Countermeasure against Transistor, Device Characteristic Deviation Thin Layer Thinning Process Treatment with No Stress / Handling Technology
The thin wafer is consisted with DZDenuded Zone: layer and there is no Gettering effect of impurities.

Realization of Highly Reliable Device with No Device Characteristic Deviation To Establish Wafer ProcessRemaining Stress Balance Design TechnologyStressor
9

BMD

(Bulk Micro Defect Layer)

Barrier against External ContaminationFormation of Damaged Layer

July, 2009

19

�2009 Association of Super-Advanced Electronics Technologies

- R&D on Thin Wafer Technology

FY2008 R&D Results

Realization of Highly Reliable Device or Process Method with Least Characteristic Deviation Blade dicing and ultrashort lasers can be used for
(1) Results of evaluating dicing of ultrathin wafers
Backside chipping Wafer thickness Blade DBG Breaking Ultrashort laser Plasma Judgment criterion 10m
Thought to be

10um thick wafer dicing , from the perspective of Transverse Rupture Strength(TRS).
Quality TRS Chip cracking 10m � �
Thought to be

Adhesive deposit 10m
Thought to be

30m

10m Measurement impossible

30m � �

30m

30m

Overall judgment

� �

Plan to reevaluate 10m 1,000MPa None None

(2) Results of evaluating backside polishing thickness of ultra-thin wafer (Target value: 10um�1um) Thickness deviation
Confirmed thickness deviation within wafer of 0.9um after glass demounting. Better control of precision is necessary. Will examine need for mechanisms to correct tolerances of glass and adhesive.
July, 2009
Wafer finished thickness

10um

30um

50um

Remark
Thickness deviation including glass Chip thickness deviation

After glass Intra-wafer attachment
Inter-wafer Inter-wafer

After BG

Intra-wafer

After glass Intra-wafer separation
Inter-wafer

0.63.3um 5.9um 0.9um

0.83.5um 8um 8 m 1.22.4um 1.74.4um 6.7um 7.1um 6.7 m 7.1 m 2.9um

20

�2009 Association of Super-Advanced Electronics Technologies

- R&D on Demonstration Devices

R&D Themes

3A1Design and Development of Demonstration Device (One proposal)
(1)Study and Development Using Basic
Demonstration Device Example Component Circuitry, System Investigation and Research in order to Realize High Speed Image Processing System of 10,000 frame/sec (2)System Investigation and Research about Demonstration Device

[Example of demonstration device]

CMOS image sensor layer AD converter layer Frame memory layer Processor layer

Example In order to conduct high speed image calculation with parallel block method, evaluate restructuring memory logical space among blocks and review the feasibility of the memory architecture.

Ultra High Speed Image Data Output more than 10,000 frames /sec Multiple Parallel One Screen frame Image Process Block Process High Speed Pipeline Process within Image Process Block from Image Sensor Layer to Processor , Calculation Circuitry Layer (3)Investigation and Research about Interface Establish mechanical and electrical interface which enables mutual connection of CMOS semiconductor device , functionality device, etc.
July, 2009

21

�2009 Association of Super-Advanced Electronics Technologies

- R&D on Demonstration Devices

R&D Themes

(32) Process Development of Demonstration Device Integration Process for 300mm Wafer
(1) Investigation and Research of TSV Formation Technology The technology to form micro TSV with diameter5um, pitch10um using Via-Last Method. (2) Research and Development of Process Integration Technology Technological development of 2 � 5 layers stacking of the device with micro TSV of over 10,000/chip formulation between chips( chip to chip, chip to wafer) or between wafers( wafer to wafer)



July, 2009

22

�2009 Association of Super-Advanced Electronics Technologies

- R&D on Demonstration Devices/Device Design

FY2008 R&D Results

Desirable structure and dimensions were determined through design studies in FY2008

TSV 35m 30m 30m 1030m 10m 70m pitch Organic substrate interposer

TSV 5m

35m pitch Sensor chip CDS chip ADC Chip Reconfigurable SRAM chip Interface chip

110m pitch

Vision of prototype for FY2010
Image sensor layer CDS S/H layer ADC layer Reconfigurable processor

This large scale frame memory is not included in the plan for FY2010
Interposer
Memory

Sensor/ADC

Frame memory

Processor

July, 2009

23

�2009 Association of Super-Advanced Electronics Technologies

- R&D on Demonstration Devices/Process Development

FY2008 R&D Results

1. Demonstration device process flow (TSV formation: Via Last/Back Via system)
TSV Device Interface chip etc. Underfill

Surface bump formation -Size: 5um~ Water lamination and underfilling Wafer thinning -Si thickness: 10um~

TSV formation -Pitch: 10um~ -Size: 3um~ -Quantity: 10,000~/C Back side bump formation -Size: 5um~

Wafer stacking finished - 4~5 layers

Singulation Repeat

2. Demonstration line is under construction

Examples of installed equipment

Bumping system

SAT and other measuring equipment

July, 2009

24

�2009 Association of Super-Advanced Electronics Technologies

Subscribe
x