GRC University Research Highlights July 2007

GRC University Research Highlights July 2007

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Research Highlights for the Month of July 2007 Computer Aided Design & Test Sciences Technical Thrust: Logic & Physical Design Research Highlight: Effective Power Optimization Combining Placement, Sizing, and Multi-Vt techniques Power dissipation is quickly becoming one of the most important limiters in nanometer IC design as leakage increases exponentially as the technology scales down. However, power and timing are often conflicting objectives during optimization. This report proposes a novel total power optimization flow under performance constraint. Instead of using placement, gate sizing, and multiple-Vt assignment techniques independently, the researchers combine them together through the concept of slack distribution management to maximize the potential for power reduction. The goal of placement and gate sizing is to achieve better slack distribution such that more effective Vt-assignment can be done afterwards. The team tested the algorithm on a set of manually optimized circuits from a multi-GHz 65nm microprocessor in an industry-strength setting, and obtained very promising results. The authors proposed a new linear programming (LP) based placement and the geometric programming (GP) based gate sizing formulations to improve the slack distribution, which maximize the power reduction in Vt-assignment stage. To the best knowledge, this is the first work that combines placement, gate sizing and Vt swapping systematically for total power (and in particular leakage) management. Univ. of Texas/Austin SRC GRC Contact: W. Dale Edwards (

Research Highlight: Report on the Evaluation of Techniques such as Gate Length Biasing, Stack Forcing and V(t)/V(dd)/T(ox) Assignment for Yield Maximization The authors present a novel technique to solve the simultaneous threshold voltage and gatelength assignment problem. The team formulated the problem in a continuous manner and show that the optimal solution has a very large proportion of the total gates already assigned to one of the available threshold voltages and lengths. The researchers snap the few remaining gates heuristically. The main contribution of this work is providing a formulation that can be solved efficiently by a general purpose non-linear optimizer to obtain a discrete multi-V(th) and multi-L solution without the added penalty of heuristic discretization. The optimization procedure is thus more effective than sensitivity-based or separate sizing and Vth/Length-assignment methods proposed previously. Circuits optimized by the proposed technique have 30-35% lower leakage and ~10% lower total power on average than circuits optimized using a sensitivity-based algorithm. Univ. of Michigan SRC GRC Contact: W. Dale Edwards ( GRC is a program of Semiconductor Research Corporation P.O. Box 12053, Research Triangle Park, NC 27709

Research Highlight: Report on the Cell Timing and Leakage Modeling under LithoInduced Variations This report summarizes work on developing an accurate model for the realistically shaped gates. There are several limited works on the device and circuit characterizations for the post-OPC nonideal-shape wafer images, with significant impacts on timing and power. Most of them, however, are based on the equivalent gate length models, which are different for timing and leakage, and thus hard to use for coherent circuit simulations. This work proposes a unified post-litho device characterization model and circuit simulation for timing and power. To the best of the researchers' knowledge, this is the most accurate methodology for post-litho analysis, including timing, leakage and transient simulation. Based on this method, the parameter extraction is also included in the model which was omitted by previous works. A post-litho model card is proposed for circuit simulation to combine these two techniques. Experimental results validate the new model. Univ. of Texas/Austin SRC GRC Contact: W. Dale Edwards ( Research Highlight: Technical Report Describing RT Constraints and Methodology, and How to Interface RT with Commercial CAD Relative timing (RT) constraints are inherent in many novel circuits for advanced clocking and GALS systems that offer performance and power advantages. However, their lack of support by commercial CAD tools severely limits their applicability. This task is focused on using commercially available static timing analysis tools for timing sign-off of RT constraints that have been identified and verified via another task, jointly removing a significant roadblock for the more wide-spread application of these circuits. This document describes a methodology for STA on two template-based asynchronous circuit families: pre-charge half buffer (PCHB) and multi-level domino (MLD) as well as extensions to non-template based circuits used by the Intel capital funded company Silistix Inc. Univ. of Southern California SRC GRC Contact: W. Dale Edwards ( Research Highlight: Report on the Improvements to Our User Interfaces to Support Industry Standard Netlists and Productivity This research task extends the relative timing verification engine with interfaces to more industry standard netlists and tools, enhancing productivity and adoption of relative timing. Formal models of circuit templates are automatically generated from structural verilog netlists, which support customized cell libraries. The relative timing engine that generates the formal proof of correctness of an implementation against a specification is being rewritten into C++ from Common Lisp, and OA integration of the modules has begun. These improvements will enable the adoption of the tool by SRC members. Further, several new circuit families have been proven correct with timing constraints. Univ. of Utah SRC GRC Contact: W. Dale Edwards (

Research Highlight: Moving Length-Scale Phenomena Upward In Design This paper reports on examples from various lateral length scales where area/performance tradeoffs are important, feasible and advantageous to be treated during design rather than as a post-design compensation. The intent of this paper is to support the overarching goal of addressing the challenge of carrying out design through the concept, design building and completed layout phases by facilitating the consideration of the presence of length dependent effects from the eventual physical layout on the manufacturing cost, yield, power, and performance including their variations and well as averages. A top down overview is given first of the integration challenges and infrastructure issues associated with including length scale effects in design. This is followed by an overview of emerging new leverages including parameter specific test patterns, automated electrical testing, and suggestions for use of attributes facilitating trade-offs in area, power and performance during design build. The main body of the report is a bottom up view of the potential physical sources of variation at the chip design level in the manufacturing process. This is divided into lithography and non-lithography considerations. The lithography considerations include the resist, lens, illumination, and mask and their interaction at the length scale of several to ten printed feature sizes. The nonlithography considerations looks at plasma etching, CMP, stress, diffusion and the important new discovery of rapid thermal anneal as a dominate source of performance variation. Here feature dependent effects are noted in etching transport and deposition rates. Effects of a few features sizes occur in stress and are likely in diffusion. Pad asperities of 40 um dominate polishing and species diffusion of 50-200 um dominat etching. Depending on the source of heating RTA can be affected by energy coupling (>100 um) and energy transport across the device structure (feature size). Univ. of California/Berkeley SRC GRC Contact: W. Dale Edwards ( Research Highlight: Report on the Technique for Timing Optimization in Placement Timing is one of the most important objectives in IC design. As interconnect delay is a significant factor in circuit timing in advanced processes, placement, which determines interconnect length and hence delay to a large extent, becomes a critical step in optimizing circuit timing. An extremely fast and high-quality technique for timing-driven Steiner tree generation is successfully developed in this task. This technique employs a table-lookup idea to efficiently generate a good Steiner tree topology. The paper reporting the technique is nominated for the Best Paper Award of ASPDAC 2007. This technique can be incorporated into any placement algorithms to guide the placement engine to produce timing-driven placement solutions. A student partially supported by this task, has been working in IBM Austin Research Laboratory as a technical co-op since February 2006 to integrate this as well as other timingdriven placement techniques into the IBM internal placer CPlace. Iowa State University SRC GRC Contact: W. Dale Edwards (

Research Highlight: Report on the Technique for Runtime Improvement in Placement As placement algorithms are repeatedly called inside a physical synthesis flow and circuit sizes are steadily increasing, techniques to reduce the runtime of placement algorithms are very important. Two techniques to improve the runtime of FastPlace are successfully developed in this task: An extension of FastPlace to a multilevel framework. The runtime is improved because the circuit size is significantly reduced in the upper levels of the multilevel framework. A twolevel framework is employed which is done by an initial netlist based fine-grain clustering followed by a netlist and location based coarse-grain clustering. A new linearization technique called Force-vector Modulation. This linearization technique nullifies the top 5-10% of spreading forces for the subsequent quadratic placement step. It allows the quadratic approach to generate a better-quality coarse placement so that the runtime it takes for iterative local refinement stage to improve the placement quality can be significantly reduced. The paper reporting the Force-vector Modulation technique is nominated for the Best Paper Award of DAC 2007. Iowa State University SRC GRC Contact: W. Dale Edwards ( Research Highlight: The Application of the CSM-Based Timing Calculator to Improving the Accuracy of Dynamic Power Dissipation Analysis in the Presence of Noise The actual shape of the voltage signal waveform at the input and output of cell should be considered in order to precisely calculate the dynamic power. In particular the short circuit current is highly dependent on the input and output voltage values. Therefore the energy dissipation due to short circuit current can be much higher in the presence of noise such as capacitive crosstalk. In this report an accurate model is presented to calculate the short circuit energy dissipation of logic cells. Previous approaches such as the approximation of the crosstalk induced noisy waveforms with saturated ramps can lead to short circuit energy estimation errors as high as an order of magnitude for a minimum sized inverter. To resolve this shortcoming, a CSM-based timing calculator is utilized, which constructs the output voltage waveform for a given noisy input waveform. The input and output voltage waveforms are then used to calculate the short circuit current, and hence, short circuit energy dissipation. A characterization process is executed for each logic cell in the standard cell library to model the relevant electrical parameters e.g., the parasitic capacitances and nonlinear current sources. Additionally, the model is capable of calculating the short circuit energy dissipation caused by glitches in VLSI circuits, which in some cases can be a key contributor to the total circuit energy dissipation. Experimental results show an average error of about 1% and a maximum error of 3% compared to SPICE for different types of logic cells under noisy input waveforms including glitches while achieving a huge run time speed-up. Univ. of Southern California SRC GRC Contact: W. Dale Edwards ( Research Highlight: Timing and Leakage Optimization Considering Systematic Channel Length Variations In this report, the effect of CD variation on the cell's delay, leakage, and the trade-off between them is analyzed. The solution space available for pitch adjustments and demonstrated feasibility for tuning standard cell-based designs is explored. Univ. of California/Santa Barbara

SRC GRC Contact: W. Dale Edwards ( Research Highlight: Placement of On-Chip Decoupling Capacitors The primary objective of the project is the development of an effective design methodology for determining the location and magnitude of a system of distributed on-chip decoupling capacitors. Focus has been placed on solving certain specific problems. A new criterion has been developed to characterize the efficiency of on-chip decoupling capacitors to reduce on-chip power noise an effective radius of an on-chip decoupling capacitor. The magnitude of the individual decoupling capacitor within a system of distributed decoupling capacitors has also been determined based on the local electrical characteristics of the power grid, substrate, and active switching loads. Related topics such as high density MIM capacitors, ground gridding, and the minimum on-chip decoupling capacitance required to satisfy target performance objectives has been included as part of the design methodology for effectively placing on-chip decoupling capacitors. Univ. of Rochester SRC GRC Contact: W. Dale Edwards ( Technical Thrust: Test & Testability Research Highlight: Seed Selection to Increase Defect Coverage for LFSR-ReseedingBased Test Compression This is a companion report to the paper recently published in the 2007 European Test Symposium. LFSR reseeding is used in many test compression solutions. A seed can be computed for each test cube by solving a system of linear equations based on the feedback polynomial of the LFSR. Despite the availability of numerous LFSR-reseeding-based compression methods in the literature, relatively little is known about the effectiveness of these seeds for unmodeled defects. Encouraging results, detailed in the companion paper, have been obtained using the output-deviation measure of the resulting patterns as a metric to select appropriate LFSR seeds. Duke University SRC GRC Contact: William H. Joyner ( Technical Thrust: Verification Research Highlight: A TLA-Based Prototype Tool for Verifying TMs In this reporting period, the task was to construct a prototype TLA module to verify that a given abstraction relation indeed suffices to show that the implementation is correct. Univ. of Illinois/Chicago SRC GRC Contact: William H. Joyner (

Research Highlight: Report on the Coverage-Directed Stimuli Generation Algorithm Based on the Partitioned State Space The main disadvantage of simulation-based methods is that the simulation vectors may only traverse a small portion of all possible scenarios, and may miss important corner cases. Generating more vectors indiscriminately often would not hit these corner cases either, since a hard-to-reach state may require careful guidance in order for the test generator to produce the effective stimuli to reach the target. Virginia Tech SRC GRC Contact: William H. Joyner ( Device Sciences Technical Thrust: Analog & Mixed Signal Research Highlight: Modeling Dynamic Avalanche Effects for Advanced Bipolar Transistor Circuit Design Up to now most work has been done on enhancing multidimensional avalanche modeling. A novel reduction technique has been developed and using it 3-dimensional quasi-distributed bipolar transistor model has been simplified and its complexity reduced. Besides, a simple diode breakdown model has been developed and is intended to model base-collector junction avalanche breakdown. NDA between DUT and Texas Instruments Inc. has been recently signed and the modern devices are expected to arrive during this summer. Afterwards there are planes to focus on measurements that will show advanced avalanche effects which are going to be followed with modeling attempts. Delft University of Technology SRC GRC Contact: Kwok Ng ( Technical Thrust: Compact Modeling Research Highlight: BSIM4.6.1 BSIM4 model is improved to describe the sub-32nm CMOS technologies accurately to enable short term technology/circuit design and long term product design. The model can be inserted any commercial circuit simulator or Berkeley Spice environment to be used for circuit simulation. Univ. of California/Berkeley SRC GRC Contact: Kwok Ng ( Technical Thrust: Device Sciences Modeling & Simulation Research Highlight: Report on the Consistent Set of Interatomic Potentials Characterized and Tested with Ab-Initio Calculations Bond-order potentials have been developed for a range of impurities in silicon (F, As and B). The potentials were parameterized by matching forces and energies to DFT calculations. Univ. of Washington SRC GRC Contact: Kwok Ng (

Research Highlight: Report on Development of a Dedicated Version of MCUT for Fast Mobility Calculations, and the Initial Work to Develop of a 3-D Version of MCUT A brief description of work to adapt "Monte Carlo UT" (MCUT) for fast mobility calculations and to 3-D device geometries is presented. The former work is essentially completed while the latter is work is just beginning. Illustrative simulation results for each are presented. Univ. of Texas/Austin SRC GRC Contact: Kwok Ng ( Research Highlight: Level Set Modeling of the Modeling of the Orientation Dependence of Solid Phase Epitaxial Regrowth This paper shows that Level Set Methods can be used to model Solid Phase Epitaxial Regrowth. The model incorporates orientation dependence of regrowth as found by Csepregi (3) The orientation dependent velocity data is taken from (3) and fitted to a polynomial function to give the growth velocity for Level Set Methods. Simulations show the capability of the model in predicting the pinching of the corners in direction and hump-like shape in direction. This is confirmed by the TEM pictures from recent papers. This modeling holds special interest because of the different diffusivities of boron in amorphous and crystalline Silicon (~5 orders of magnitude difference) and because of the various defects forming at the pinching corners which could lead to higher leakage current in scaled devices. The Level Set Model is implemented in FLOOPS (Florida Object Oriented Process Simulator). Univ. of Florida SRC GRC Contact: Kwok Ng ( Research Highlight: Effect of Low Ge Content on B Diffusion in Amorphous SiGe Alloys Diffusion of B in amorphous Si is known to be 4 orders of magnitude higher than in crystalline Si. The effect of Ge at low concentrations on B diffusion in the amorphous phase is unknown. 1.5-micron thick relaxed layers of varying SiGe alloys (0, 6, 12, 100 at % Ge) were grown on Si. After growth the layer was amorphized to a depth of 0.8-micron using a 500 keV 5x10(15)on/cm( 2) Si+ implant at 77K. Next a 500 eV 1x10(15) ions/cm(2) B+ implant was introduced. The amorphous SiGe was recrystallized at temperatures between 300�C and 600�C and the B diffusion during solid phase epitxial regrowth (SPER) was studied using dynamic secondary ion mass spectrometry (SIMS). Comparison of B diffusivities for amorphous Si and amorphous Si0.88Ge(0.12) revealed similar activation energies (2.7 and 2.8 eV respectively) and pre-exponential factors (0.8 and 4.8 cm(2)/s respectively). The negligible change in B diffusion in amorphous SiGe at low Ge concentrations is similar to reports on B diffusivity for strainrelaxed crystalline SiGe alloys with Ge content. These results suggest that Ge is not an effective trap for B in the amorphous phase. Univ. of Florida SRC GRC Contact: Kwok Ng ( Research Highlight: Simulation of Electronic Transport in `Unconventional' MOSFETs This report summarizes theoretical results regarding: Different aspects of the density-of-states bottleneck in 20 nm InGaAs MOSFETs, highlighting the role of "source starvation" in the quasiballistic limit; A new formulation of scattering with surface roughness in thin bodies, extending Ando's model including roughness at both interfaces; The role of scattering with high-k phonons

in short-channel devices, showing that the mobility degradation does not lead to a corresponding degradation of the on-current; Electron mobility in III-V channels and quantum wells; And, finally, preliminary calculations of the hole mobility in Ge inversion layers, employing a new hybrid scheme to account for self-consistent effects using a 6-band k*p model. Univ. of Massachusetts SRC GRC Contact: Kwok Ng ( Research Highlight: Construction of the Structure of Si(110)/a-SiO(2) Interfaces with and without Uniaxial Strain This research aims to develop predictive kinetic models for ultrashallow junction formation in strained silicon (Si) channels with amorphous thermal silicon dioxide (a-SiO(2)) gates, needed for rational experimental designs for the 45-nm node or beyond. Using first principles-based atomistic modeling, this theoretical program concentrates on developing a deeper understanding of the structure and dynamics of defects and defect-dopant complexes in strained Si as well as at the interfaces of strained-Si with a-SiO(2). This report summarizes the construction of thermally favored c-Si(110)/a-SiO(2) interface structures with varying uniaxial strain, using Continuous Random Network based Metropolis Monte Carlo (CRN-MMC) simulations. The model structures will further be used to examine the annihilation of native defects as well as the precipitation of dopants at the c-Si/a-SiO(2) interfaces. Univ. of Texas/Austin SRC GRC Contact: Kwok Ng ( Research Highlight: Report on the Regrowth Simulations of Material with Multiple Impurities Based on Accurate Interatomic Potentials This document reports on studies of recrystallization of Si doped with F and B which have been computationally modeled through molecular dynamics simulations in order to explore impurity redistribution (diffusion and segregation) and regrowth kinetics. Univ. of Washington SRC GRC Contact: Kwok Ng ( Research Highlight: Report on the Atomistic Simulations of B Diffusion in Amorphous Si as Function of B and F Concentrations This document reports on molecular dynamics studies of B and F diffusion in amorphous and crystalline silicon. Univ. of Washington SRC GRC Contact: Kwok Ng ( Technical Thrust: Digital CMOS Research Highlight: Report on the Ultra-Fast Pulse Generator This report summarizes recent progress in developing an ultra-fast transmission line pulsing system that can be used to characterize the breakdown voltage of gate dielectrics in the 100ps regime. It has been reported that ESD-CDM (Electro Static Discharge - Charged Device Model) events can induce high voltage pulses with approximately 100ps pulse widths on transistor gates in the core. However, there has been no direct measurement of dielectric breakdown voltage in this regime. This is partly due to the fact that commercial pulse generators are only capable of generating pulses with pulse-width greater than 1ns. In order to characterize dielectric

breakdown voltages in the 100ps regime, an ultra-fast transmission line pulse generator was developed, and has been demonstrated to be capable of producing sub-100ps pulses Stanford University SRC GRC Contact: Kwok Ng ( Research Highlight: Physics of Strain Effects in Semiconductors and Metal-OxideSemiconductor Field-Effect Transistors A detailed theoretical picture is given for the physics of strain effects in bulk semiconductors and surface Si, Ge, and III-V channel metal-oxide-semiconductor field-effect transistors. For the technologically important in-plane biaxial and longitudinal uniaxial stress, changes in energy band splitting and warping, effective mass, and scattering are investigated by symmetry, tightbinding, and k � p methods. The results show both types of stress split the Si conduction band while only longitudinal uniaxial stress along Univ. of Florida SRC GRC Contact: Kwok Ng ( Research Highlight: Flexure Based Wafer Bending Setup: User's Guide This is a user guide to Flexure Based Wafer Bending Setup. Univ. of Florida SRC GRC Contact: Kwok Ng ( Research Highlight: Hole Mobility in Silicon Inversion Layers: Strain and Surface Orientation Hole transport in the p-type Metal-Oxide-Semiconductor Field-Effect-Transistors (p-MOSFETs) inversion layer under arbitrary stress, surface and channel orientation is investigated by employing a six-band k-p model and finite difference formalism. The piezoresistance coefficients are calculated and measured at stress up to 300 MPa via wafer-bending experiments for stresses of technological importance: uniaxial and biaxial stress on (001)- and (110)-surface oriented p-MOSFETs with and channels. With good agreement in the measured and calculated small stress piezoresistance coefficients, k-p calculations are used to give physical insights into hole mobility enhancement at large stress (~3 GPa). The results show that the maximum hole mobility is similar for (001)/, (110)/, and (110)/ p-MOSFETs under uniaxial stress, although the enhancement factor is different. For (001) p-MOSFETs, the dominant factor for the improved hole mobility is reduced conductivity effective mass at small stress and lower phonon scattering rate at large stress. Strong quantum confinement and a low density-of-states (DOS) cause less stress-induced mobility enhancement for (110) p-MOSFETs. Univ. of Florida SRC GRC Contact: Kwok Ng ( Research Highlight: Preliminary Study on New Contact Materials on Boron Doped SiGe Alloys This report presents the results of a preliminary study on platinum germanosilicide contacts formed on SiGe alloys. The focus of this study was to explore the impact of the germanosilicide layer on the in-plane strain in the SiGe layer. This information is important because the band structure of SiGe is a strong function of this strain, hence, any variations in the strain distribution might lead to variation in the Schottky barrier height, an essential parameter for contact resistivity. The experiments were performed on SiGe alloys with 28 and 50% Ge. Different

thicknesses of Pt were used to form the germanosilicide layers. Raman spectroscopy and X-Ray diffraction analysis were used to study the strain distribution in SiGe. The experimental results indicate that platinum germanosilicide does not change the strain distribution in SiGe within the limits of our measurement methods. North Carolina State University SRC GRC Contact: Kwok Ng ( Research Highlight: Epitaxy of Si(1-x)C(x) Alloys from Disilane and Trimethylsilane This report presents preliminary results obtained on epitaxy of Si(1-x)C(x) alloys using the precursors disilane and trimethlysilane. The results indicate that the growth temperature must be reduced while the total pressure must be increased to maximize the substitutional carbon incorporation. The highest substitutional carbon level obtained in this study was approximately 1.3% obtained at 575 degrees Celcius with a growth rate of 6 nm/min. North Carolina State University SRC GRC Contact: Kwok Ng ( Research Highlight: Report on Three-Dimensional Composition and Defect Structure of Novel Metallic Alloy Silicides Laser assisted local-electrode atom-probe (LEAP�) tomography is used to map the threedimensional distribution of Pd atoms in nickel monosilicide thin films on Si(100). A solid solution of Ni(0.95)Pd(0.05) on Si(100) was subjected to rapid thermal processing and stationary-state annealing treatments to simulate the thermal processing experienced by NiSi source and drain contacts in CMOS processing. Pd is found to segregate to the (Ni(0.95)Pd(0.05))Si/Si interface, thereby decreasing its interfacial Gibbs free energy. The concomitant reduction in the driving force for phase change and agglomeration leads to an increase in the thermal stability window for NiSi. The root-mean-squared chemical roughness of the interface is determined to be 0.783 nm. Northwestern University SRC GRC Contact: Kwok Ng ( Research Highlight: High-Resolution Work-Function Measurements Using Kelvin-Probe Force-Microscopy (KPFM) Kelvin-Probe Force Microscopy (KPFM) was performed to spatially resolve variations in work function on NiSi and CoSi(2) samples. Work function was found to be very uniform (�15 meV) across the scanned area for both the NiSi as well as the CoSi(2) sample. Work function measurements from two independent AFM's were in agreement with each other and with previously reported values. KPFM has been demonstrated as a unique tool which addresses the pressing need for metal gate work function characterization as mentioned in the ITRS 2005 and 2006 update editions. Northwestern University SRC GRC Contact: Kwok Ng ( Research Highlight: Pattern Dependency of Selective Epitaxy of SiGe-Based Materials Grown by RPCVD The authors have established a model for epitaxy of SiGe:B with input parameters (T, P, Gas Ratios) and the growth rate and film composition as output parameters. Furthermore, a layout for selective epitaxy growth has been presented. All epi-layers were elevated but the team has

applied it for recessed openings with 120- 200 nm. The researchers have investigated the process conditions for maximizing B-doping in selective SiGe:B. The optimum values are following: 3-5 x 10(20) cm(-3) in SiGe layers with Ge content of (26-31%). A layout model for monitoring pattern dependency of SiGe layers has been presented. Royal Institute of Technology (KTH) SRC GRC Contact: Kwok Ng ( Research Highlight: Report on W-Based Gate Electrodes on Hf-Based High-k Dielectric This study examines three different W-based electrode gate stacks for use in MOSFETs. Each stack represents a different stage in the formation of a W/Si(x)/high-k/Si stack. The first sample is only metallic W/high-k/Si. The second sample has a layer of amorphous silicon on top of the W layer. The third sample is the thermally treated form of the second sample W/Six/high-k/Si. The goal of this study is to determine if any unreacted metallic Tungsten is present in the third sample (nominally the WSi(x) gate) by comparison of all three stack structures. Univ. of Texas/Dallas SRC GRC Contact: Kwok Ng ( Research Highlight: Initial Report on Interdiffusion Behavior and Interface Stability Issues for Metal/High-K/Strained Si Gate Stacks This report reviews recent studies of the compositional profile and interdiffusion of high-K gate stacks on III-V substrates. A central requirement in the integration of III-V substrates in highly scaled CMOS gate stacks is to develop an ability to assure that the researchers create a high capacitance, high mobility transistor structure with a low concentration of defects. The authors have explored sulfur passivation methods to help ensure that the starting III-V surface (InGaAs in this case) has a low defect concentration. Rutgers University SRC GRC Contact: Kwok Ng ( Research Highlight: Final Report Summarizing Research Accomplishments on Hf-Based Metal Gate Stack Stability Research This final report summarizes the major projects performed under this task including: (1) the study of the thermal stability of Ni-based FUSI films on Hf-based high-k materials, (2) the study of the thermal stability of La-capped Hf-based high-k dielectrics, and (3) an evaluation of WSi(x) formation on Hf-based dielectrics. Each study is described in detail in this final report. Univ. of Texas/Dallas SRC GRC Contact: Kwok Ng ( Research Highlight: Sub-22 nm III-V MOS Transistor Development This report summarizes process flow development and the present status of the fabrication process used by the SRC NCRC in fabrication of III-V MOSFETs. The process flow includes modules for gate definition, gate sidewall formation, extrinsic source-drain formation by regrowth, self-aligned source-drain contact deposition, mesa isolation, and a routine interconnect back-end. Existing III-V HEMT fabrication processes readily enable fabrication of 20-40 nm length gates. Fabrication of short-gate-length III-V MOSFETs is much more difficult, as self aligned N+ source-drain regions must be formed, and the process must scale to 22 nm gate length. No III-V MOS process reported in the literature meets these requirements--- the process development here reported is both novel and highly challenging. The key process modules are

gate stack and sidewall, extrinsic source/drain, planarization, and interconnect back-end. The gate stack & sidewall process is nearly completed, as is the planarization sequence. Source-drain regrowth is now under intensive development at both UCSB and Minnesota. The interconnect back-end process is routine. Finally, the four process modules must be integrated into an overall fabrication sequence. Univ. of California/Santa Barbara SRC GRC Contact: Kwok Ng ( Technical Thrust: Memory Technologies Research Highlight: Report on the Development of Optical Lithography 1-10 um Diameter Junctions The development work reported here, has produced a nanofabrication process flow for making testable resistance change vias from simple three-film stacks. Focused ion beam etching has been used instead of optical lithography because of its rapid turnaround and flexibility. A necessary step in this process is an Ar ion etching step to clean Ga contamination from sidewalls. Without this step shorting between top and bottom electrode is observed. Via sizes to 500 nm are straightforward with this process, and initial testability of these electrical structures has been demonstrated. Carnegie Mellon University SRC GRC Contact: Kwok Ng ( Integrated Circuit & Systems Sciences Technical Thrust: Circuit Design Research Highlight: Report on the Application of MLSE for High-Speed I/O Links State-of-the-art I/O link transceivers employ various forms of equalization to compensate for intersymbol interference (ISI) and noise. These receivers make decisions on a symbol-by-symbol basis. Maximum likelihood sequence estimation (MLSE) makes decisions on symbol sequences and hence can achieve the same bit error-rate but at a lower signal-to-noise ratio (SNR) as compared to a symbol-by-symbol detector. This report presents a comparison of symbol-bysymbol and MLSE detection for I/O links. Univ. of Illinois/Urbana-Champaign SRC GRC Contact: W. Dale Edwards ( Research Highlight: Wideband Frequency Synthesizers for Future Wireless Communication Systems This report summarizes the design challenges associated with wideband synthesizers, prior work on bandwidth widening techniques and novel wideband fractional-N PLL approaches proposed by this project. All of the second year commitments of the proposal have been met, and an overall architecture for a very low noise sigma delta fractional-N frequency synthesizer is defined. Circuit level topologies for all of the building blocks have been defined, and system level simulations utilizing Simulink and SpectreAMS have been started. A brief summary of the proposed innovations for this three year project is as follows: Instead of conventional tri-state phase-frequency detectors (PFD) where a charge-pump injects a phase error proportional current into a capacitor, a voltage-mode PFD is designed. This addresses several shortcomings

associated with current-mode PFDs in deep submicron processes. Residual control word from the digital noise shaper is utilized to discharge the loop filter using a digitally controlled resistorstring to remove the quantization induced phase noise from the VCO control line. A selfregulated VCO is designed to minimize supply noise impact on VCO phase noise for SOCs. Emerging broadband wireless standard WiMAX requires a frequency tuning range from 2.5GHz to 5.5GHz. The proposed architecture utilizes a single VCO to cover the wide tuning range. The Ohio State University SRC GRC Contact: W. Dale Edwards ( Research Highlight: Global On-Chip Serial Signaling - A Report on Circuit Techniques and Documentation of Prototype Design With the increase in clock frequencies to multi-GHz rates, using conventional parallel bus-based communication it has become impossible to move data across a die in a single clock cycle. There are also reliability problems due to timing errors, skew, and jitter in fully synchronous systems. Noise, coupling, and inductive effects become significant for both intermediate length and global routing. Serial on-chip links are an attractive alternative. This report describes new circuit techniques used in an on-chip global serial link scheme. Simulations of a prototype link implemented in 0.13um CMOS are also given. Univ. of Michigan SRC GRC Contact: W. Dale Edwards ( Research Highlight: Report on Circuit Design and Layout This report summarizes the circuit design and layout of a fully integrated, four-antenna, 5GHz Alamouti Transmitter. The transmitter uses a direct conversion architecture with a single phaselocked loop (PLL) to generate a quadrature 5.4GHz LO signal for all four data paths. Figure-8 inductors are used in the PLL's VCO and injection locked dividers to help mitigate parasitic coupling from the inductive load of the power amplifiers. Total die size is 3mm � 5mm and it is fabricated in a 0.18�m CMOS process. Univ. of Washington SRC GRC Contact: W. Dale Edwards ( Research Highlight: System Study Report This report focuses on a system level study of the embedded ADC calibration technique developed in this research. Focus is placed on nonidealities, robustness and practicality within a typical RF environment. Stanford University SRC GRC Contact: W. Dale Edwards ( Research Highlight: Report on ADC Implementation and OFDM Tests This report describes the design and implementation of a 6-bit CMOS ADC prototype demonstrating the proposed system-embedded calibration technique. In addition to circuit level details, this report includes test results of the ADC operating within an emulated UWB OFDM system. Stanford University SRC GRC Contact: W. Dale Edwards (

Research Highlight: Hybrid Noise Shaping for Oversampling D/A Conversion This report summarizes the latest results and conclusions from a study of architectural alternatives for an approach to over sampling digital-to-analog conversion that is based on using a hybrid cascade of digital and analog noise-shaping modulators. By embedding a reconstruction filter, as well as the actual D/A interface, within a feedback loop, it appears that the linearity and timing accuracy requirements for the interface can be significantly relaxed, enabling operation from a low supply voltage and with considerable savings in power. Stanford University SRC GRC Contact: W. Dale Edwards ( Research Highlight: Evaluation of FSL LDMOS Transistors for High Efficiency Class AB RF Stages for Use in Drain Modulation Systems Drain modulation amplifiers are RF/microwave power amplifiers which employ time-varying power supply voltage in order to improve their power efficiency. This report summarizes measurements of LDMOS transistors provided by Freescale in a drain modulation system at UCSD. Excellent results, with overall power-added efficiency reaching 48%, were obtained for representative WCDMA signals with peak-to-average power ratios of 7.8dB. Overall average RF output power was 42W, and peak power was 250W. To the author's knowledge, these results correspond to record efficiency for LDMOS transistors in a WCDMA base station amplifier application. Univ. of California/San Diego SRC GRC Contact: W. Dale Edwards ( Research Highlight: Report on the Design of Low Power Decoders for Memory Circuits with Intrinsic Leakage Control Conventional memory address decoders based on static CMOS gates suffer from high clock loading, delay, and unnecessary power dissipation in unselected banks. The dynamic decoder presented here has 29% lower address to word line delay and 34% lower active power than a conventional decoder. The design leverages the predictability of dynamic circuits to provide over 20x leakage reduction in unselected banks. The dynamic decoder is implemented on a 90 nm process. The measured test chip address to word line delay is 170 ps at 1.5 V. Arizona State University SRC GRC Contact: W. Dale Edwards ( Research Highlight: Innovative On-Chip Thermal Sensor Calibration Techniques This document outlines the basics of calibration and the issues pertinent to the field of on-chip thermal sensing. The researchers have described the related work in this field and delved into some of the ideas that can be borrowed from the calibration problem in wireless networks to our domain. The authors have identified 5 parameters that can be the fundamental sources of variation in a thermal sensor reading and explained the reason for their occurrence as well as the nature of their variation. The researchers have proposed an innovative thermal sensing technique that can sense temperature at both the interconnect level and the substrate level called IBOTS (Interconnect based Oscillator for Thermal Sensing). The team has used regression analysis to describe the dependencies of the sensor output on the parameters identified. The research team has used a metric called "measurement error" to determine the allowable range of frequency

values that are to be assigned to individual temperature values. Some of the prominent research challenges that we have identified in the on-chip thermal sensor calibration problem are: (1) Extraction of exact die temperature profile in the post-packaging environment (2) Accurate modeling of parameter variations in a thermal sensing circuit and isolation of different noise sources (3) Incorporation of calibration logic in the sensor support circuitry (4) Minimization of number of fuses needed for calibration (5) Development of test-bed to validate a specific calibration approach (6) Development of generic calibration approach for a particular class of thermal sensors (e.g. frequency output thermal sensors) and also, in the face of systematic "drift" in sensor circuit performance Univ. of Massachusetts SRC GRC Contact: W. Dale Edwards ( Research Highlight: Report on the Measured Results of Design of 10-Gsamples/s Nyquist A/D Converter with Embedded DFE This report reviews the architecture of a serial link receiver that is based on a 5-bit pipeline A/D converter operating at 5GS/s. The converter further embeds a mixed-signal decision feedback equalization to reduce the required resolution of the A/D for compensating bandwidth limitations. The receiver has been implemented and the measurement results are reported. The anticipated performance at 4.8GS/s has been achieved for the A/D converter while dissipating