Are you ready for 32nm?

Are you ready for 32nm?

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Description: Topics discussed: IBM Technology Roadmap, Improved Gate Length Scaling with High-k / Metal Gate, 32/28LP HKMG Technology, SRAM Vmin improvement with High-k, Scaling on Mixed Signal / RF Key Figures of Merits, High Performance 28G Technology, Physical IP is more than NAND gates, Moore’s Law and Consumer Expectations, ARM 32nm Test Chip Program Objectives, 32nm Test Chip Overview, Litho-driven Interconnect Optimization, 32 nm vs. 45 nm: Test Chip Results and more. .

 
Author: Dr. Jaga Jagannathan, Dr. Rob Aitken, Dr. Vassilios Gerousis (Fellow) | Visits: 2575 | Page Views: 2617
Domain:  High Tech Category: Semiconductors Subcategory: 32nm 
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Contents:
Are you ready for 32nm?
Moderator Ana Molnar Hunter, Vice President of Foundry, Samsung Semiconductor Speakers Dr. Jaga Jagannathan, Director, 32/28 Technology Productization, IBM Semiconductor R&D Center Dr. Rob Aitken, Fellow, Research & Development, ARM Dr. Vassilios Gerousis, Senior Architect, Cadence Design Systems

32nm / 28nm Technology
Dr. Jaga Jagannathan Director 32/28nm Technology Productization IBM Semiconductor R&D Center

Our Goal: Provide value to our clients through leadership technology

IBM Technology Roadmap
15 nm Generations of technology Leadership for Low Power (LP) & High Performance(HP) markets 22 / 20 nm 32 nm /28 nm 45 nm 65 nm 90 nm 130 nm
Logic-based embedded DRAM HKMG Tinv scaling 3D devices HKMG Tinv scaling Computational Scaling Litho High-k gate dielectric Third Generation e-SiGe Embedded n-fet Strain

Advanced Strain Engineering Ultra Shallow Junction Engg. Ultra Low-k metal dielectrics Immersion lithography

Strained silicon / DSL Embedded SiGe Liners / Metallization Low-k dielectrics

180 nm
Silicon-on-Insulator

250 nm

Copper interconnect

Su

e in a st

d

n io t va no in

in

M IB

n ch te

o

gy lo

Denotes Common Platform Mfg Process

� 2009 ARM Limited, Cadence Design Systems, and IBM. All Rights Reserved Worldwide

Improved Gate Length Scaling with High-k / Metal Gate
300 Equivalent Oxide Thickness (nm) Metal Gate High-k 10 100 90 40nm 1
80 70 60 50 40 30

200 Gate Length (nm)

30nm

1.15 nm

20

10 250 180 130 90 65 45 32MGHK Metal High-k
-

Technology Node (nm)
Transistor length scaling stopped at 90 nm node High-K/MG re-enables traditional transistor scaling

Interface layer Si

� 2009 ARM Limited, Cadence Design Systems, and IBM. All Rights Reserved Worldwide

32/28LP HKMG Technology
� Gate-last HK-MG presents significant process
Complexity
complexity

�Simplified gate-first process without eSiGe &
DSL provides cost benefit & is more DFM friendly

Gate-First HK-MG process flow
Channel engineering High-k dielectric dep. Gate dielectric engineering Metal & polysilicon dep. Gate patterning Extension implants Spacer formation S/D implantation Activation anneal Ni Salicidation ESL deposition

Relative Process Complexity (%)

Relative Process Complexity (%)

STI, Wells & VT implants

Lower complexity (4-5%) for Lower complexity (4-5%) for 32LP vs other gate options 32LP vs other gate options
105 104 103 102 101 100 99 98 32 nm HKMG 32 nm SiON

Simplified & Cost Effective

Realizable with optimized HKMG module and without eSiGe stressor
� 2009 ARM Limited, Cadence Design Systems, and IBM. All Rights Reserved Worldwide

SRAM Vmin improvement with High-k
Calculated Vt sigma for PD nfet Calc Vt sigma for PDNFET by tech node per technology node
60

Vt~Tox/(WxL)1/2 1.5 Normalized Vt Mismatch Poly-SiON 40%

45nm
45nm 65nm 65nm 32nm 32nm

56.25

1 0.5

Vt sigma (mV)

52.5

48.75 calc Vt sigma (mV)

HK/MG 0 7.0 9.0 11.0 13.0 1/sqrt (WXL) 15.0

45

41.25

90nm 90nm

37.5

33.75

30

1.5

2

2.5 Tinv (nm)

3

Fail counts (64Meg)

1000 100 10 1 0.1 0.01 0.001 0.0001 0.7

HK/MG Poly-SiON

1.5

2.0

2.5 tinv (nm)

3.0

� 40% reduced Vt mismatch with Tinv scaling � ~180mV Vmin improvement over Poly/SiON

180mV Vmin improvement

0.8

0.9

1

1.1

1.2

Vdd (V)

� 2009 ARM Limited, Cadence Design Systems, and IBM. All Rights Reserved Worldwide

32LP Hardware-Validated AC-Vdd Performance
10
3

Star = Alpha Corner Targets

RO Delay (ps/stage)

RVT Ring Osc.(126nm Pitch)
10
2

SS FF
10
1

0.5

0.6

0.7

0.8 0.9 Vdd (V)

1

1.1

1.2

� FO=3 Inverter ring show functionality down to Vdd=0.6V, enabling Dynamic-Vdd, PowerPerformance Management designs � Performance margins for low-Vdd can be increased with LVT and SLVT device use

� 2009 ARM Limited, Cadence Design Systems, and IBM. All Rights Reserved Worldwide

32LP HKMG is Now Deployed for Partners & Customers Technology Readily Migratable to 28nm
Leadership 32nm High-k/Metal Gate technology available to designers now
Process Design Kits ready Committed to market leadership both in design access & production volumes Excellent Technology transfer results on matching IBM HKMG from first lots Includes shrinkable rules to 28nm with similar performance and power/area

Focus on early customer IP development
MPW shuttles available for partners & early customers First 3 shuttles "sold out"

Excellent industry reception & client feedback

MPW MPW1 MPW2 MPW3 MPW4 MPW6

Process SOLD32LP OUT 32LP, 32G SOLD OUT SOLD OUT 32LP, 32G 32LP 28 nm compatible

DRC Clean GDSII Oct 08 Feb 09 Jun 09 Nov 09 1H 10

� 2009 ARM Limited, Cadence Design Systems, and IBM. All Rights Reserved Worldwide

32nm Customer Feedback
First 32LP MPW wafers delivered to multiple customers. ARM featured first 32LP wafer at Mobile World Congress, Barcelona (Feb 2009) Positive client Feedback "Extremely strong 32nm LP offering and seen as a leader" "This technology is excellent" "IBM Alliance's HK/MG technology is competitive choice that will create healthy disruption in the industry "

� 2009 ARM Limited, Cadence Design Systems, and IBM. All Rights Reserved Worldwide

28LP SRAM (Industry Leading Density)
1.2 1.0V 1.0 0.8 Vout[V] 0.6

0.120 SRAM array
0.4 0.2 0.0 0.00

0.20

0.40

0.60 Vin[V]

0.80

1.00

1.20

Excellent cell stability with HKMG SNM of ~210 mV at VDD = 1 V

SRAM S120 cell

� 2009 ARM Limited, Cadence Design Systems, and IBM. All Rights Reserved Worldwide

Scaling on Mixed Signal / RF Key Figures of Merits:
28 nm mixed signal & RF capabilities:
Scaling of ft:


New material supports scaling of mixed signal / RF IP in all aspects. Excellent Performance increase, transit frequency ft up to 300GHz Beol capacitor density increase / flicker noise decrease enable shrink ability of RF IP





Beol capacitor density:

Measurement results: nFET ft data

Flicker Noise:

� 2009 ARM Limited, Cadence Design Systems, and IBM. All Rights Reserved Worldwide

High Performance 28G Technology
Built on LP platform with added Strain elements & Tinv scaling
Elements common with IBM High Performance SOI Technology Integrating HKMG with performance elements 26nm gate length ; reduced Vt mismatch

Migrating to 28 G HKMG (building on 28nm LP)
Attractive Power, Performance, Area & schedule with any competing 28G 1 BEOL using 28 LP process
0.8

bit-cell matrix PG

PD PU

V OUT [Volt]

0.6

0.4

0.2

Cell size < 0.15um2 Vdd = 0.9V SNM = 210mV

0 0 0.2 0.4 0.6 0.8 1

V IN [Volt]
� 2009 ARM Limited, Cadence Design Systems, and IBM. All Rights Reserved Worldwide

Summary
Leadership Performance 32nm Low Power High-K / Metal Gate Available Now
Beta PDK 7/31/2009 Technology Migratable to 28nm; Eval models available Now

MPW parts delivered to early customers; Follow on MPW's sold out
IP ecosystem partners ARM, Cadence & Others part of the Collaborative Innovation Ecosystem

Delivering Industry Leading Si Technology to Clients
Expanding Partnership; Continues success of "Collaborate to Innovate" model Unparalleled Resources deployed to ensure thriving innovation ecosystem
Albany Nanotech 300mm research facility; NYS Packaging Initiative

Solid Exploratory Technology Road map to 22nm / 15nm
Computational lithography to extend immersion optical Lithography Novel device architectures; New materials & Process innovation

� 2009 ARM Limited, Cadence Design Systems, and IBM. All Rights Reserved Worldwide

32nm / 28nm Physical IP
Dr. Rob Aitken, Fellow Research & Development, ARM

ARM @ 32nm
ARM has been working on 32nm designs since early 2008 32LP physical IP products under development
On schedule for release later this year

Multiple chip tapeouts at ARM Increasing design complexity, but silicon success

� 2009 ARM Limited, Cadence Design Systems, and IBM. All Rights Reserved Worldwide

Physical IP is more than NAND gates
15+ foundries Up to 8 process generations per foundry Up to 11 variants in each generation 6+ memory generators 900+ standard cells per library 200+ I/Os 10+ views per cell Plus PHY, analog IP, etc.

300+ libraries per year, each with thousands of individual data elements
� 2009 ARM Limited, Cadence Design Systems, and IBM. All Rights Reserved Worldwide

Moore's Law
Original Paper:
"Cramming more components onto integrated circuits" Electronics, 38-8, 4/19/65

Tracks changes from 1959 to 1965 and predicts trend going forward It's still going...

� 2009 ARM Limited, Cadence Design Systems, and IBM. All Rights Reserved Worldwide

Moore's Law and Consumer Expectations
Product Customer Expectation Technology
CPU: 8-bit Z-80 processor, 1.05 MHz Screen: 2.6" 160 x 144 LCD 4 b/w Connectivity: 4 players by serial cable

Price

$169

Nintendo GameBoy (1989)
CPU: ARM9TM (133 MHz), ARM7TM (33MHz) Screen: Two 3" 256 X 192 color LCDs, 256MB Flash, AAC audio, 2 VGA cams Connectivity: Wifi, browser, shopping

$169

Nintendo DSi (2008/2009)

>1000x performance for the same price
� 2009 ARM Limited, Cadence Design Systems, and IBM. All Rights Reserved Worldwide

Cooperation at 32nm HKMG
High K metal gate process is a significant break through/change from previous processes CP and ARM recognized that superior optimization and leverage could be obtained with early engagement Interaction was designed to occur at multiple levels
Design rules Electrical behavior CPU performance

4 ARM tapeouts with CP at 32LP node

� 2009 ARM Limited, Cadence Design Systems, and IBM. All Rights Reserved Worldwide

ARM 32nm Test Chip Program Objectives
Demonstration of early collaboration and innovation Feedback and influence Design Rules at 32nm HKMG Demonstrate cells/IP in an embedded CPU application Quantify PPA across the design
Especially dynamic and leakage power

Statistical design investigation
Quantify margins

Have early understanding at this new process generation
Translate to superior products for current and future ARM processors Silicon data used in product development
ARM 32LP R&D Test Chip #2 TO - Q4'08, Si - Q1'09

� 2009 ARM Limited, Cadence Design Systems, and IBM. All Rights Reserved Worldwide

32nm Test Chip Overview
Mux
GPIO CortexM3 WatchDog UART Local Memory AHB Memory Controller WatchDog UART Local Memory AHB Memory Controller GPIO CortexM3 WatchDog UART Local Memory AHB Memory Controller GPIO CortexM3 WatchDog UART Local Memory AHB Memory Controller GPIO CortexM3 WatchDog UART Local Memory AHB Memory Controller GPIO CortexM3

Mux JTAG Clocks

R&D structures

External Flash

External SRAM

All functional in silicon!

� 2009 ARM Limited, Cadence Design Systems, and IBM. All Rights Reserved Worldwide

Benefits of Early Engagement
Relative Frequency versus Baseline 104.0% 102.0% 100.0% 98.0% 96.0% 0.75V 94.0% 92.0% 90.0% 88.0% 86.0% 84.0%
Approach 1 Approach 2 Approach 3 Approach 4 Approach 5 Approach 6

0.8V 0.9V 1.0V 1.1V 1.2V

Compare relative performance of multiple architectures for 12 track standard cells
� 2009 ARM Limited, Cadence Design Systems, and IBM. All Rights Reserved Worldwide

32nm Test Chip Results: CPU paths
Shows GHz range processors feasible in 32LP silicon
Performance vs Voltage, CPU paths, 25C
2000 1800 1600 1400 F (MHz) 1200 1000 800 600 400 200 0 0.75V 0.8V 0.9V 1.0V 1.1V 1.2V Path 1 Path 2 Path 3 Path 4

� 2009 ARM Limited, Cadence Design Systems, and IBM. All Rights Reserved Worldwide

Working with Cadence
Cadence worked on 32nm testchip based on ARM CortexTM-M0 processor (Vasillios' talk) ARM 32nm standard cell library
Tested interoperability of Cadence NanoRoute with ARM standard cells Early work on LEF technology file

Learning derived from project
Router interoperability with CP 32nm rules Observations on cell architecture Silicon proof point � Oct 2009
� 2009 ARM Limited, Cadence Design Systems, and IBM. All Rights Reserved Worldwide

DA C 200 9 Pan el Are you

Summary
ARM has significant experience at 32nm (and below)
4 - 32LP tapeouts, others in process End-to-end design flows implemented Early and ongoing interaction with Common Platform to co-optimize process, IP Currently working on 28nm, 22nm nodes

� 2009 ARM Limited, Cadence Design Systems, and IBM. All Rights Reserved Worldwide

32nm / 28nm EDA Technology
Dr. Vassilios Gerousis Advanced Technology, Digital Implementation

Cadence Design Systems

EDI System Readiness To Support 32/28 nm CP LP HKMG
� Support for complex 32/28 nm rules. � High frequency routing � Model based analysis & Optimization (CMP, Litho, and Stress).

Advanced Layout Rules

Manufacturing Aware Design

Design Closure
Variation Aware Design
� Analysis & Optimization: �MMMC, �SOCV, �SSTA/SI

Timing/SI/PI Power Area Manufacturability

High Speed and Big Design
� Hierarchical design � Variation aware clock � Multi-core support

� 2009 ARM Limited, Cadence Design Systems, and IBM. All Rights Reserved Worldwide

Readiness for CP 32/28 nm Layout Rules and Libraries

NanoRoute routing rules implemented
100% rule coverage Verified by Cadence in tape-outs including ARM Cortex-M0 and by multiple customers Demonstrated routability and runtime improvements of ARM library (dense libraries)

Additional implementation tools are also ready such as Virtuoso Space-based Router (VSR), and YieldPlus OpenAccess is updated to support latest rules
Updated IC 6.1 PDK OA enables interoperability between EDI and Virtuoso to support mixed-signal and custom design
� 2009 ARM Limited, Cadence Design Systems, and IBM. All Rights Reserved Worldwide

Litho-driven Interconnect Optimization
Prevention
Encounter
Litho hotspot prevention

Key Benefits:
Industry's only hybrid grid & space-based route optimization solution Very fast litho hot spot checking (qualified for 32nm) � NEW
Integrated in Encounter

Analysis

Signoff Litho Verification with Litho Physical Analyzer

Incremental

Hotspots & Guidelines

Key Features:
Litho-aware routing prevention and correction Incremental optimization, correction and checking

Fixing

Encounter
Litho hotspot correction

Litho Clean Interconnect

� 2009 ARM Limited, Cadence Design Systems, and IBM. All Rights Reserved Worldwide

Statistical Design for Timing/SI and Leakage
1.40E-04 1.20E-04 1.00E-04 SLPA Monte Carlo

W NE

8.00E-05 6.00E-05 4.00E-05 2.00E-05 0.00E+00 -2.00E-05 0 10000 20000 30000 40000 50000 60000

Leakage
Leakage Power (uW)

Statistical SI (S-SI)

Design For Variability
(Analysis & Optimization)
6 4

Statistical Leakage Power

Delay
Statistical STA

2

0

1.3 1.4
Dela1.5 y(ns )

-10.0 1.6 -10.4

JPDF of power and delay
� 2009 ARM Limited, Cadence Design Systems, and IBM. All Rights Reserved Worldwide

lo g( Le ak ag e)

-9.2 -9.6

Hybrid Clock Structure
Improving variation and power Symmetric and balanced structure delivers minimum OCV sensitivity tight skew minimum insertion delay Potential for lower power Multiple clock mesh structures to meet wide variety of area, timing, and power targets Gated mesh for dynamic power control Fast and automatic mesh synthesis and built-in mesh analysis
local tree clusters

� 2009 ARM Limited, Cadence Design Systems, and IBM. All Rights Reserved Worldwide

32 nm Silicon-Correlated Models
Collaboration between Cadence and IBM CP on "early" silicon engagement. Architected and built two 32 nm test chips in the Common Platform MPW Utah Chip: CMP modeling Description: Test chip for characterizing systematic variation in CMP process 6mm x 2mm M1 to M8: varying density and width Purpose: data collected from silicon will be used to build CMP model V-Chip: variability modeling Description: testchip for characterizing systematic and random variability for device and interconnect Purpose: silicon characterization of variations (types, magnitude, etc.) to correlate that with internal modes and tool features
� 2009 ARM Limited, Cadence Design Systems, and IBM. All Rights Reserved Worldwide

32 nm vs. 45 nm: Test Chip Results
�Working results from both U-Chip (CMP Modeling) V-chip (Device Modeling) �Created 32 nm CMP model using measured data from the test chip. �CMP modeling feedback �Less Relative Copper Loss at 32 nm vs 45 nm �Higher variability in 32 nm vs 45 nm �V chip feedback �Random variability component dominates systematic components (i.e. Stress & Litho) �A third test chip was taped-out on the next MPW's

� 2009 ARM Limited, Cadence Design Systems, and IBM. All Rights Reserved Worldwide

Preliminary Stress Variation Results
Vtplin % Variability (L=0.03/W=0.6)
% Random vtplin % Systematic vtplin

Liner

Vertical Active d

LOD (defined by Poly)

Contact & Poly Space

T-GATE (litho)

� 2009 ARM Limited, Cadence Design Systems, and IBM. All Rights Reserved Worldwide

Horizontal Active d

U-ACT (litho)

LOD

Summary
Encounter Digital Implementation System (EDI) is ready support 32/28 nm CP LP HKMG 32/28 nm layout rules and ARM library support are verified through tape-outs 32 nm Early silicon engagement with Common Platform
Two Test Chips: Silicon correlation on Variability and CMP models to the process technology Cadence is ready to address both 32 nm DFM (CMP, stress and litho) and random variability through SSTA and S-SI analysis and optimization On-going collaboration with CP in next MPWs

� 2009 ARM Limited, Cadence Design Systems, and IBM. All Rights Reserved Worldwide

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