SOC Architecture and Design

SOC Architecture and Design

Loading Social Plug-ins...
Language: English
Save to myLibrary Download PDF
Go to Page # Page of 24

Description: Topics discussed include how computers are driven by semiconductor advances, SOC vs real processors on a chip, Two views of a processor, The programmerís view: the instruction set architecture and The designerís view: the micro-machine, Sequential and parallel machines, Array processors, Vector processors, Interconnects and buses and more.

Author: Wayne Luk (Fellow) | Visits: 2108 | Page Views: 2122
Domain:  High Tech Category: Semiconductors Subcategory: SOC 
Upload Date:
Short URL:

px *        px *

* Default width and height in pixels. Change it to your required dimensions.

SOC architecture and design
� processor: a component in system: system-on-chip (SOC) � system: includes special-purpose processors, cache and memory, interconnect and design aids � need to know
� � � � � � � � � user view of the variety of processors basic information about technology and tools processor internals and the effect on performance cache and (embedded and external) memory evaluating basic systems (processor, cache, memory) system functions and specialized processors design productivity and reconfiguration system interconnections (buses and switches) wl 2010 9.1 system modelling

Computers: driven by semiconductor advances
Transistors per die 10,000,000,000
cost per transistor 1 0.1 0.01 0.001 0.0001 0.00001 0.000001 Cost

100,000,000 T r a n s is to r s 1,000,000 10,000 100 1 1960 1970 1980 1990 2000 2010 Year

0.0000001 1968




wl 2010 9.2

SOC vs real processors on a chip
� with lots of transistors, designs move in 2 ways:
� system on chip (or die) � processor(s) with lots of cache SOC
processor cache memory functionality interconnect multiple, simple, heterogeneous one level, small embedded (on die) specialized applications wide, fast on die

Processors on chip
few, complex, homogeneous 2-3 levels, extensive very large, off die general purpose limited bandwidth slow limiting factor
wl 2010 9.3

wl 2010 9.4

Two views of a processor
The programmer's view: the instruction set architecture

The designer's view: the micro-machine

wl 2010 9.5

Processor type: overview
Processor type Architecture / Implementation approach SIMD Vector VLIW Superscalar Single instruction applied to multiple functional units Single instruction applied to multiple pipelined registers Multiple instructions issued each cycle under compiler control Multiple instructions issued each cycle under hardware control
wl 2010 9.6

Adding instructions
� additional instructions to support specialized resources
� exception: superscalar

� instructions can be added to base processor for coprocessor control
� VLIW � Array � Vector
wl 2010 9.7

Processors for SOCs
Freescale c600: signal processing ClearSpeed CSX600: general PlayStation 2: gaming ARM VFP11: general

Basic ISA

Processor description
Superscalar with vector extension Array processor with 96 processing elements Pipelined with 2 vector coprocessors Configurable vector coprocessor

Proprietary MIPS


wl 2010 9.8

Sequential and parallel machines
� basic single stream processors
� pipelined: basic sequential � superscalar: transparently concurrent � VLIW: compiler generated concurrency

� multiple stream
� array processors � vector processors

� multiprocessors
wl 2010 9.9

Pipelined processor

wl 2010 9.10

Superscalar and VLIW processors
Instruction #1 IF Instruction #2 IF ID Instruction #3 IF Instruction #4 IF ID Instruction #5 IF Instruction #6 IF ID AG DF EX WB ID AG DF EX WB AG DF EX WB ID AG DF EX WB AG DF EX WB ID AG DF EX WB


wl 2010 9.11



wl 2010 9.12

Array processors

One instruction issued to all processor units

Control unit

Sp < N

N processing units, each with own local memory; neighbor communications
wl 2010 9.13

Array processors
� perform op if condition = mask � operand can come from neighbor
mask op dest sr1 sr2

wl 2010 9.14

Vector processors
� vector units include vector registers, typically 8 regs x 64 words x 64 bits � vector instructions: