The Case for Monolithic 3-D Flash

The Case for Monolithic 3-D Flash

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Description: Topics covered such as trends in NAND Flash and the challenges of NAND Charge Trap Flash. The case for Monolithic 3-D Flash and the Wish List for Monolithic 3-D Flash as well as the challenges of 3-D NAND Charge Trap Flash. Then the Schiltron Solution is explained giving the physical structure, electrical results, comparisons, and conclusions.

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Author: Andrew J. Walker (Fellow) | Visits: 4172 | Page Views: 4258
Domain:  High Tech Category: Semiconductors Subcategory: Flash 
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Contents:
DG-TFT-SONOS 3-D Flash
Andrew J. Walker
Schiltron Corporation Mountain View, CA

Schiltron Corporation - IEDM 2008

Outline of Presentation
� � � � � � � � � � Trends in NAND Flash Challenges of NAND Charge Trap Flash The Case for Monolithic 3-D Flash Wish List for Monolithic 3-D Flash Challenges of 3-D NAND Charge Trap Flash The Schiltron Solution Explained Physical Structure Electrical Results Comparisons Conclusions
Schiltron Corporation - IEDM 2008

Trends in NAND Flash
� Floating gate approach coming to an end at ~2X nm gate length:
� Floating gate interference � Unable to scale tunnel oxide � Unable to scale interpoly dielectric

� Shift to Charge Trap Flash (CTF):
� TANOS � Bit-Cost Scalable (BiCS) Flash

Schiltron Corporation - IEDM 2008

Challenges of NAND Charge Trap Flash
Inversion Layer To Bitline

Vread-pass

Vread

Vread-pass

ONO

N+

N+

N+

N+

� Vread-pass > Vtprog + margin � Vprog-pass > Vtprog + margin

Pass disturbs on selected string

� Apply to both lateral and vertical NAND CTF
Schiltron Corporation - IEDM 2008

Challenges of NAND Charge Trap Flash
Floating Gate problems Charge Trap Flash Minimize Read-pass disturb Thicken tunnel oxide (VARIOT ?)

Maximize worstcase string OPTIMIZATION RESULTS: current Thicken tunnel oxide (VARIOT ?)

� High program/erase voltages � Limited endurance � Read-pass disturb � Challenging MLC � Scalability ?
Need high program voltage Use high WF gate (TaN)

Need high erase voltage

Minimize program and program-pass disturb

Thicken blocking oxide (use Al2O3)

Schiltron Corporation - IEDM 2008

The Case for Monolithic 3-D Flash
1 0.9

64Gbit; 2D: 25nm, Do=0.1/cm2, AE=75%, MLC 3D: 32nm, MLC, varying Do Do=0.1/cm2 Do=0.05/cm2

3D/2D Cost

0.8 0.7 0.6 0.5 0.4 0.3 1

Do=0.01/cm2
2 3 4 5

Do=0.02/cm2
6 7 8

Number of Device Layers
A.J. Walker, "A Manufacturing Cost Model for 3-D Monolithic Memory Integrated Circuits" to be published by IEEE Transactions on Semiconductor Manufacturing
Schiltron Corporation - IEDM 2008

Wish List for Monolithic 3-D Flash
� � � � � � � � Laterally scalable Easily stackable Reasonable program/erase voltages High program bandwidth Good endurance Good retention MLC capability All at low cost
Schiltron Corporation - IEDM 2008

Challenges of 3-D NAND Charge Trap Flash � Lateral Channel Solutions:
� Thick ONO to alleviate pass disturbs � High program/erase voltages
� Need special 3-D source/channel contact for erase

� Read-pass disturb limits number of reads � Challenging MLC � Scalable ? :
� Single gated MOS with thick gate dielectric
Schiltron Corporation - IEDM 2008

Challenges of 3-D NAND Charge Trap Flash � Vertical Channel Solutions
� Gate all-around with channel hole to substrate � Scalable ? :
� F > 2 X (CTF dielectric thickness)

� Serious selected string read-pass disturb � Very challenging MLC � Stackable ? :
� Worst-case string current halves for every doubling of NAND string length and density � Pass disturbs in selected string worsen
Schiltron Corporation - IEDM 2008

The Schiltron Solution Explained
Inversion Layer To Bitline
N+ N+

Vread
N+

2nd Gate ONO
N+

1st Gate

Vread-pass
� Double-gate approach

Off

Vread-pass

� Close electrostatic interaction for short channel control and lateral scalability � Electrical shielding of memory charge from pass voltages
Schiltron Corporation - IEDM 2008

The Schiltron Solution Explained
Gate2
Vs

Vds Drain Inversion channel Gate1 Vgs

Source

Source Depletion region Electric field lines Gate1
Schiltron Corporation - IEDM 2008

Gate1 dielectric

The Schiltron Solution Explained
� Consequences:
� Laterally scalable with DG structure � ~ Zero pass disturbs � Worst-case string current decoupled from Vread-pass � Thin ONO

Schiltron Corporation - IEDM 2008

Physical Structure

32 cell string after channel trench etch
Schiltron Corporation - IEDM 2008

Physical Structure

64 cell string after 2nd gate formation
Schiltron Corporation - IEDM 2008

Physical Structure

XTEM perpendicular to wordline gate direction

Schiltron Corporation - IEDM 2008

Physical Structure

48nm gatelength

350 A channel thickness

XTEM perpendicular to wordline gate direction
Schiltron Corporation - IEDM 2008

Physical Structure

XTEM perpendicular to channel direction

Schiltron Corporation - IEDM 2008

Physical Structure

45nm channel width "nanowire"

XTEM perpendicular toIEDM 2008 channel direction Schiltron Corporation -

Physical Structure � Source/Drain
1E+20

Sb Concentration (/cm3)

800oC 1min
1E+19

825oC 1min

1E+18

As implanted
1E+17
0 20 40 60 80 100 120

Depth into Silicon (nm)
Schiltron Corporation - IEDM 2008

Physical Structure � Source/Drain
Sheet Resistance (Ohm/sq)
2000 1800 1600 1400 1200
Anneal Time = 1 min

1000 500 550 600 650 700 750 800 850 900

Anneal Temperature (oC)
Schiltron Corporation - IEDM 2008

Electrical Results � Single DG Device
Source-Drain Current (A) 10-6 10-7
2V 4V 3V 2nd Gate Voltage -4V -3V -2V

2nd

10-8
1V

10-9 10-10 10-11 10-12
-2 -1 0 1

W/L = 50nm/65nm 0V -1V dch ~ 35nm Vds = 0.5V
2 3 4 5

1st

1st Gate Voltage (V)
Schiltron Corporation - IEDM 2008

Pass Disturb
2nd Gate Vt (V)
4 3 2 1 0 1 10 100 1000
Programmed Memory Cell

N+

N+

Vpass = 9V

Duration of 9V Application to 1st Gate
Schiltron Corporation - IEDM 2008

Stored charge is immune to pass voltages

Worst-Case String Current
64 cell Dual-Gate string (W/L = 45nm/48nm Devices)
Midcell Gate voltage

Bit Line

OFF

OFF

Source

ON with read pass voltage OFF

ON with read pass voltage

Schiltron Corporation - IEDM 2008

Worst-Case String Current
Worst-Case String Current (A) 10-7
64 cell string W/L = 45nm/48nm dch ~ 35nm Vds = 1V

8V

7V

6V 5V 4V 3V

10-8
Read-pass V

10-9
Mid-cell 1st gate at -3V All memory devices off except mid-cell

2V

10-10
-1 0 1 2 3 4 5

2nd Gate Voltage on Mid-Cell (V)
Schiltron Corporation - IEDM 2008

Worst-Case String Current
Worst-Case String Current (nA) 200 180 160 140 120 100 80 60 40 20 0
0
Read-pass V
64 cell string W/L = 45nm/48nm dch ~ 35nm Mid-cell 1st gate at -3V Mid-cell 2nd gate at 3V All other memory gates off

8V 7V 6V 5V 4V 3V

0.5

1

1.5

2

String Source-Drain Voltage (V)
Schiltron Corporation - IEDM 2008

Worst-Case String Current
Worst-Case String Current (nA)
800 700 600 500 400 300 200 100 0 2 4 6 8
16 cells 32 cells 64 cells
W/L = 45nm/48nm dch ~ 35nm Mid-cell 1st gate at -3V Mid-cell 2nd gate at 3V All other memory gates off

String Length 8 cells

Read-Pass Voltage (V)
Schiltron Corporation - IEDM 2008

Mid-Cell Threshold Voltage (V)

Cycling Endurance
4 3.5 3 2.5 2 1.5 1 10 100 1000 10000 100000
W/L = 45nm/48nm 32 cell string dch ~ 35nm Vprog/Verase = 17.5V 100us / -13V 400ms Read-pass voltage = 7V Program-pass voltage = 7V Erase-pass voltage = 6V

Number of Cycles
Schiltron Corporation - IEDM 2008

Retention After Cycling
Threshold Voltage (V)
4 3.5 3 2.5 2 1.5 1 0.5
1.0E+00 1.0E+01 1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07 1.0E+08 1.0E+09

After 105 cycles 10 years

0

Time at 85oC (s)
Schiltron Corporation - IEDM 2008

Comparisons
ATTRIBUTE Pass Disturb Worst-Case String Current Scalability

TANOS
Strong dependence on Vpass

BiCS
Very strong dependence on Vpass Strongly limited by read-pass disturb Limited by need to have thick enough memory dielectric in hole Limited by decreasing worstcase string current Very challenging due to pass disturbs

Schiltron
~ Zero Independent of read-pass voltage so can be maximized Inherently scalable DG structure

Limited by readpass disturb

Limited by Vprog and single-gated 3D device structure

Stackability MLC

Has been shown Challenging due to pass disturbs

Can be done

Path identified

Schiltron Corporation - IEDM 2008

Conclusions
� Schiltron DG-TFT-SONOS:
� Laterally scalable due to DG structure � Easily stackable due to S/D dopant "freezing" � Reasonable program/erase voltages due to independent ONO scaling � High program bandwidth due to tunneling � Good endurance due to thin tunnel oxide � Good retention even after cycling � MLC capability due to disturb stability � CMOS-friendly materials used throughout

Schiltron Corporation - IEDM 2008

Contact
� � � � � Andrew Walker PhD Schiltron Corporation www.schiltron.com andy@schiltron.com Tel: +1 408 425 4150

Schiltron Corporation - IEDM 2008