Reliability and Yield Issues in Nano-Scale Technologies

Reliability and Yield Issues in Nano-Scale Technologies

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Description: Paper covers: MOS Devices and Circuits. Sources & Types of Variations. scaling.

Line Edge Roughness (LER). Discrete doping. Discrete oxide thickness.

R and V body distributions. Self-heating. Hot spots.

IR drops. Layout Dependent Systematic Variations. Design rules effect on Performance.

Reliability & Yield. RDF: Random Dopant Fluctuations. HCI: Hot Carrier Stress.

Electromigration. Transient Faults. RTS and Digital Circuits.

 
Author: Prof Gilson Wirth, UFRGS (Fellow) | Visits: 2202 | Page Views: 2225
Domain:  High Tech Category: Semiconductors Subcategory: Yield Management 
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Contents:
Reliability and Yield of MOS Devices and Circuits
Prof Gilson Wirth UFRGS - Porto Alegre, Brazil

This set of slides is a summary of the lecture. The lecture may be tailored to the needs and interest of the audience, and composed by a larger set of slides. The lecture covers new phenomena which play a role on the performance and reliability of highly scaled MOS devices. Performance and reliability become influenced also by factors other than physical dimensions. Furthermore, variations of parameters over time (aging and transient effects such as noise and soft errors) may lead to dramatically increased overhead in the timing budget, as well as on test procedures. We need to understand the underlying physical mechanisms, and develop analysis and modeling techniques to support IC designers. Among the effects discussed in this lecture, the major ones are: - Parametric variability due to effects such as random dopant fluctuations and line edge roughness. - Aging effects such as Bias Temperature Instability (BTI), Hot Carrier Injection (HCI), Electromigration and Time Dependent Dielectric Breakdown (TDDB). - Radiation Effects, such as Single Event Transients (SET) and Single Event Upsets (SEU). - Device intrinsic noise, with focus on the Random Telegraph Signal (RTS). A short CV and list of publications may be found at http://lattes.cnpq.br/1745194055679908

Issues in Nano-Scale Technologies
Electrical Behavior / Parameter Variation

Spatial

Temporal

Random: RDF, LER, etc

Systematic: Process Gradients, etc

Aging: NBTI, HCI, Electrom., etc

Transient: SET/SEU, Noise, etc

Designer must consider both Process and Temporal Variations
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Issues in Nano-Scale Technologies
Performance

Average Speed
Minimum Acceptable Performance Transient Error Permanent Failure

Time

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Issues in Nano-Scale Technologies
Speed

Variability

Minimum Acceptable Speed Transient Error Permanent Failure

Time

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Sources & Types of Variations
Process Global or Correlated and , , 's, , , Environment Temporal

Operating temperature range, VDD range

and

Local Or Random

Line Edge Roughness (LER), Discrete doping, Discrete oxide thickness, R and Vbody distributions

Self-heating, Hot spots, IR drops

Distribution of NBTI, HCI, Noise, Radiation Eff. (SET/SEU), Oxide breakdown currents

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Sources & Types of Variations
Process Global or Correlated and , , 's, , , Environment Temporal

Operating temperature range, VDD range

and

Local Or Random

Line Edge Roughness (LER), Discrete doping, Discrete oxide thickness, R and Vbody distributions

Self-heating, Hot spots, IR drops

Distribution of NBTI, HCI, Noise, Radiation Eff. (SET/SEU), Oxide breakdown currents

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Long Range x Short Range Variations
Frequency

Long Range Variation in VT

V
Frequency

T

Short Range Variation in VT
(also mismatch in analog circuits)

Different Averages
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V

T

Different Types of Process Variation
Total Parameter Variation

Systematic

Random

Layout and Neighborhood Dependent

Systematic Across Chip

Intra-Die

Inter-Die

Short range Mismatch
After Saxena et al, IEEE-TED 2008
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Random Across Chip

Systematic x Random

130 nm: Systematic

90 nm: More Random

Ring Oscillator Freq Variability Neuberger, Wirth el al. ESSCIRC 2006.
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Systematic Variations
Example of Layout Dependent Systematic Variations: CMP affects dense areas of lines differently than sparsely populated areas of lines.

Design Measure: Regularity and Dummies also in Digital Circuits
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Random Variations
250 180 130 90 65 45 nm

Defect limited yield

Parametric limited yield

hard fails, screenable

soft fails, sensitive to Temp / Vdd / f , difficult to screen

/ � (Area)-0.5
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Variability Increases with Scaling

Current-ratio variability of 10:1 current mirror for 130-nm, 90-nm, and 65nm technologies [Bernstein et al., IBM J. RES. & DEV., 2006].
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Pessimistic Design Hurts Performance
Performance

Average Performance

Worst Case

Is This Worth a Huge Investment?
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Technology generation

Optimistic Design Hurts Reliability & Yield
- Parametric Yield Loss - Wear Out Before End of Expected Product Life Time

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Random Process Variations
RDF: Random Dopant Fluctuations LER: Line Edge Roughness

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RDF: Random Dopant Fluctuations

The simulation Paradigm now

A 22 nm MOSFET In production 2009 A 4.2 nm MOSFET In production 2023

A Asenov et al., IEEE-TED 2003

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LER: Line Edge Roughness

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Parameters become Random Variables

[Source: S. Y. Borkar, Intel, 2004]
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Power x Timing

[Source: S. Y. Borkar, Intel, 2004]
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Power x Timing
Probability

Good chips Too leaky Too slow

Vt
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Aging
NBTI: Negative Bias Temperature Instability Shifting of PMOS Vt over time, reducing On Current HCI: Hot Carrier Injection Shifting on NMOS Vt over time, reducing On Current Electromigration Increase of Interconnect Resistance (or Rupture)

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HCI: Hot Carrier Stress
Hot carrier stress generates additional trap states near to the drain:

- Locally shifts Vt at the drain side. - Is also a source of noise. Noise relevance of traps
Source: R Brederlow, PhD Thesis
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HCI: Hot Carrier Stress
Changes in drain current [%] Changes in gate referred voltage noise [%]
103
Stress @ Vg=1.2V, Vd=5.5V

102

102
3x104 s

105 s

101

101 0.0

n-MOS W / L = 15�m / 0.75�m Characterization @ Vg= 1.2V

100 1.5

0.5

1.0

Drain voltage - effective gate voltage [V]

HCI in NMOS: Reduced On Current and Increased Noise.
Source: R Brederlow, PhD Thesis
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NBTI: Negative Bias Temp Instability

Source: K Kang et al., IEEE ICCD 2006

-Vt increases over time - Ids reduces affecting PMOS Speed.
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Design Centering Over Product Lifetime

NBTI-Aware Technique for Transistor Sizing of High-Performance CMOS Gates. M da Silva, V Camargo, L Brusamarello, G Wirth and R da Silva. LATW 2009
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HCI and NBTI
� Note that these effects are also history dependent, varying according to total time spent in the 'on' or 'off' state. � Associated with the average threshold shift, there are also random shifts. � Even for identical use conditions and devices, there are mismatch shifts due to random variations in the number and spatial distribution of the charges/interface states formed. � Small gate area devices will experience more random mismatch.

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Electromigration
� Particularly likely to affect the thin tightly spaced interconnect lines of deep-submicrometer design. � Difficult to be prevented by product testing. � Main cause: generation of stress in the grain boundaries and interfaces.

Common Failure Modes: Grain Boundaries and Interfaces.
M. A. Meyer and E. Zschech, Proc. 9th Int. Workshop Stress Induced Phenom. Metallization, 2007.

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Transient Faults
Radiation Effects: SET: Single Event Transient SEU: Single Event Upset RTS: Random Telegraph Signal Signal Integrity Issues (e.g., Noise Coupling, Substrate Noise Coupling, etc).

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Radiation Effects

Please clic on Fig to run movie
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Radiation Effects
VDD PMOS

ID
IN (GND) OUT (Vdd)

1 0 IP
NMOS

IC
CNODE

Charge Collection Mechanism
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SET in Combinational Logic
Particle strike 1 0 1 0 0 1 1 1 1 0 0 0 1 1 0 1

1 0

0 1 1 0

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SEU in Sequential Logic
WL OFF OFF WL

0 1

01

OFF

OFF

gnd

BIT-FLIP
N P N P

ionization

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Sequence of Events from Ionization to Failure

Fault latency

Error latency

+ - +++ - - ++ ionization Transient current (injected or extracted from the junction)

BIT -

FL IP

ERROR

FAILURE

Transient voltage pulse (capacitor node)

clk

FAULT

FAULT EFFECT

Fault tolerant techniques

Sensors (detection)

Time redundancy (detection, mitigation)

Hardware redundancy Error correcting codes (detection and mitigation)

Self-checking mechanisms with recovery Recomputation (detection and mitigation)

Redundancy / Spare components

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BulkBulk-BICS
Wirth et al., IEEE Micro, 2007

particles protons, heavy ions
C BI S

gnd

VDD

B

lk u

S IC -B lk Bu

++ + -- ionization

35 Gilson In�cio Wirth

RTS: Random Telegraph Signal

Trap Gate Oxide

Inversion layer

Drain Current ID

Interaction with the inversion layer

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RTS: Random Telegraph Signal

Leads to modulation of the local mobility and number of free carriers in the channel
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Variability: Dependency on Circuit Bandwidth
6,0 5,5 5,0

np/

4,5 4,0 3,5 3,0 2,5 1 10 100 1000 10000

fH/fL

G Wirth et al. IEEE Trans Electron Dev, 2007
38 Gilson In�cio Wirth

RTS: Random Telegraph Signal
S(log)

Current

c

d

e
Time

f(log)

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RTS and Digital Circuits

VT Fluctuations
40 Gilson Wirth

RTS and Digital Circuits

+ VT

-

VT Fluctuations
41 Gilson Wirth

RTS in SRAM
RTS causes instability issues on SRAM memories
RTS impact on cell characteristics: far from Normality

Accurate Model for RTS noise in digital circuits: Statistical RTS model for digital circuits. L Brusamarello, G Wirth and R da Silva. Microelectronics Reliability, 2009.
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RTS: Erratic Fluctuations of SRAM Cache Vmin at the 90nm Process Technology Node

Vmin on some SRAM arrays varied from one measurement to the next.
Source: M Agostinelli et al. (Intel), IEDM 05
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RTS in CMOS Image Sensor Pixels

Temporal output behavior of pixels
Source: X Wang, P R Rao, A Mierop, A Theuwissen. IEDM 06.
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RTS Flash Memories

FANTINI et al. IEEE-EDL December 07
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Signal Integrity Issues
Crosstalk Noise: Due to electromagnetic coupling between Signal Lines. Power/Ground Noise: Due to Simultaneous Switching of Many Gates. Substrate Noise: Signal can couple from one node to another via the substrate.

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Could Variability & Reliab. Cost Become Reliab. Show Stopper ?
Cost
Scaling Not Profitable Total Product Cost

Cost per Transistor Reliability Cost

Technology Node

High-cost reliability solutions (increased design cost, increased silicon area, etc) and service may lead to unacceptable costs.
Based on T Austin et al., IEEE D&T of Comp., 2008.
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Could Variability & Reliab. Cost Become Reliab. Show Stopper ?
Cost

Total Product Cost

Cost per Transistor Reliability Cost

Technology Node

Need for New Low-Cost, Resilient Design Methodologies
Based on T Austin et al., IEEE D&T of Comp., 2008.
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HW & SW Techniques for Enhancing Reliab. Reliab.
Application Operating Sys BIOS Intercon. & I/O H W Memory Logic
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S W

Check-point and Roll Back, Application Replication & SW Voting, Robust Data Structures, Memory Management, etc.

Space, Time and Information Redundancy & HW Voting. Sense & Correct.

Issues for Test
- Traditional Go-Don't Go Test (usually intended to screen hard failures, not Adequate - Burn-In and Iddq Test Challenged by Leakage Currents - Complex Aging Mechanisms

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Conclusion
� Process parameter variations and variations of parameters over time (both aging and transient) are very important in Nano-scale technologies � Tools for automated estimation of yield and reliability are mandatory � New design methodologies to assure yield and reliability are required � New test methodologies to coupe with parametric and transient failures needed � It is needed to simultaneously address power, speed and reliability constraints � Proper process eng., modeling, simulation and design can lead to high yield and reliability.
51 Gilson Wirth

Bibliography (to be completed)
� S Sahhaf, R Degraeve, P Roussel, B Kaczer, T Kauerauf and G Groeseneken, "A New TDDB Reliability Prediction Methodology Accounting for Multiple SBD and Wear Out", IEEE TED, VOL. 56, NO. 7, pp. 1424- 1432,JULY 2009. �Tibor Grasser and Ben Kaczer, "Evidence That Two Tightly Coupled Mechanisms Are Responsible for Negative Bias Temperature Instability in Oxynitride MOSFETs", IEEE TED, VOL. 56, NO. 5, pp. 1056-1062, MAY 2009. �W Wang, V Reddy, A Krishnan, R Vattikonda, S Krishnan Y Cao, "Compact Modeling and Simulation of Circuit Reliability for 65-nm CMOS Technology", IEEE TDMR, VOL. 7, NO. 4, pp. 509 517, DECEMBER 2007. �T Austin, V Bertacco, S Mahlke and Y Cao, "Reliable Systems on Unreliable Fabrics", IEEE Design & Test of Computers, pp. 322-333, July/August 2008. �A Asenov, A Brown, J Davies, S Kaya and G Slavcheva, "Simulation of Intrinsic Parameter Fluctuations in Decananometer and Nanometer-Scale MOSFETs", IEEE TED, VOL. 50, NO. 9, pp. 1837-1852, SEPTEMBER 2003. � A Cathignol, B Cheng, D Chanemougame, A Brown, K Rochereau, G Ghibaudo and A Asenov, "Quantitative Evaluation of Statistical Variability Sources in a 45-nm Technological Node LP NMOSFET", IEEE TED, VOL. 29, NO. 6, pp. 609-611, JUNE 2008. �A Datta, S Bhunia, S Mukhopadhyay and K Roy, "Delay Modeling and Statistical Design of Pipelined Circuit Under Process Variation", IEEE-TCAD, V. 25, NO. 11, pp. 2427-2436, NOV. 2006. �Q Chen, H Mahmoodi, S Bhunia and K Roy, "Efficient Testing of SRAM With Optimized March Sequences and a Novel DFT Technique for Emerging Failures Due to Process Variations", IEEE TVLSI, VOL. 13, NO. 11, pp. 1286-1295,NOV. 2005.

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�G Formicone, M Saraniti, D Vasileska and D Ferry, "Study of a 50-nm nMOSFET by Ensemble Monte Carlo Simulation Including a New Approach to Surface Roughness and Impurity Scattering in the Si Inversion Layer", IEEE TED, VOL. 49, NO. 1, pp. 125-132, JANUARY 2002. � Saxena et al., "Variations in Transistor Performance and Leakage in Nanometer-Scale Technologies", IEEE TED, V. 55, No. 1, pp. 131-144, January 2008. � Bernstein et al., "High-performance CMOS variability in the 65-nm regime and beyond", IBM J. RES. & DEV., pp. 433-449, 2006. � S Borkar, "Designing Reliable Systems from Unreliable Components: The Challenge of Transistor Variability and Degradation", IEEE Micro, pp. 10-16, 2005. � K Agarwal and S Nassif, "Characterizing Process Variation in Nanometer CMOS", DAC 2007, pp. 396-399, 2007. � K Kang, H Kufluoglu, M Alam and K Roy, "Efficient Transistor-Level Sizing Technique under Temporal Performance Degradation due to NBTI", ICCD 2006, pp. 216, 221, 2006. � Ehrenfried Zschech et al., "Geometry and Microstructure Effect on EM-Induced Copper Interconnect Degradation", IEEE TDMR, VOL. 9, NO. 1, pp. 20-30, MARCH 2009. � M. Agostinelli et al., "Erratic Fluctuations of SRAM Cache Vmin at the 90nm Process Technology Node", IEDM 2005, � X Wang, P Rao, A Mierop and A Theuwissen, "Random Telegraph Signal in CMOS Image Sensor Pixels", IEDM 2006. � G WIRTH, R da SILVA; R BREDERLOW. "Statistical Model for the Circuit Bandwidth Dependence of Low-Frequency Noise in Deep-Submicrometer MOSFETs". IEEE TED, v. 54, p. 340-345, 2007. � R da SILVA,; G WIRTH; L BRUSAMARELLO. "An appropriate model for the noise power spectrum produced by traps at the Si-SiO2 interface: a study of the influence of a time-dependent Fermi level". Journal of Statistical Mechanics. Theory and Experiment, v. 2008, p. P10015, 2008. � WIRTH, G. I. ; VIEIRA, Michele G ; HENES NETO, Egas ; KASTENSIMIDT, Fernanda G L . Modeling the sensitivity of CMOS circuits to radiation induced single event transients. Microelectronics Reliability, v. 48, p. 29-36, 2008. 53 Gilson Wirth

� WIRTH, G. I. ; VIEIRA, Michele G ; KASTENSIMIDT, Fernanda G L . Accurate and Computer Efficient Modelling of Single Event Transients in CMOS Circuits. IEE Proceedings. Circuits, Devices and Systems, v. 1, p. 137-142, 2007. �BRUSAMARELLO, Lucas ; SILVA, Roberto da ; WIRTH, G. I. ; REIS, Ricardo Augusto da Luz . Probabilistic Approach for yield analysis of dynamic logic circuits. IEEE Transactions on Circuits and Systems. I, Regular Papers, v. 55, p. 2238-2248, 2008. �WIRTH, G. I. ; SILVA, Roberto da . Low-Frequency Noise Spectrum of Cyclo-Stationary Random Telegraph Signals. Electrical Engineering (Berlin), v. 90, p. 435-441, 2008. �HENES NETO, Egas ; WIRTH, G. I. ; KASTENSIMIDT, Fernanda G L . Mitigating Soft Errors in SRAM Address Decoders Using Built-in Current Sensors. Journal of Electronic Testing, 2007. �WIRTH, G. I. . Bulk Built In Current Sensors for Single Event Transient Detection in DeepSubmicron Technologies. Microelectronics Reliability, v. 48, p. 710-715, 2008 �HENES NETO, Egas ; RIBEIRO, Ivandro ; VIEIRA, Michele G ; WIRTH, G. I. ; KASTENSIMIDT, Fernanda G L . Using Bulk Built-in Current Sensors in Combinational and Sequential Logic to Detect Soft Errors. IEEE Micro, USA, v. 26, p. 10-18, 2006. �SILVA, Roberto da ; WIRTH, G. I. ; BREDERLOW, Ralf . Novel analitical and numerical approach to modelling low-frequency noise in semiconductor devices. Physica. A, Inglaterra, v. 362, n. 2, p. 277288, 2006. �WIRTH, G. I. ; KOH, Jeongwook ; SILVA, Roberto da ; BREDERLOW, Ralf ; THEWES, Roland . Modeling of Statistical Low-Frequency Noise of Deep-Submicron MOSFETs. IEEE Transactions On Electron Devices, USA, v. 52, n. 7, p. 1576-1588, 2005. �WIRTH, G. I. ; SILVA, Roberto da ; KOH, Jeongwook ; THEWES, Roland ; BREDERLOW, Ralf . Noise and Fluctuations in Deep-Sub-Micron MOSFETs. Journal Of Integrated Circuits And Systems, Brazil, n. In Press, 2005. � G Wirth, R da Silva, P Srinivasan, J Krick and R Brederlow, "Statistical Model for MOSFET LowFrequency Noise under Cyclo-Stationary Conditions", IEDM 2009.

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