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On the Optimum Selection of Channel Material for Extremely Scaled FETs
Victor Zhirnov, Ralph Cavin
8th-May-2007
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On the Optimum Selection of Channel Material for Extremely Scaled FETs (An SRC Working Paper, August 7, 2006) V. V. Zhirnov and R. K. Cavin
Abstract In this paper, we develop an abstract model for a semiconductor binary switch that provides insight into parameters that, to first-order, govern the ON/OFF current ratio for the switch. One interesting result of this analysis is that as channel lengt
...
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is decreased, the optimum ON/OFF ratio is achieved by an increase in the electron effective mass. We investigate several semiconductor channel materials (e.g. Ge, and III-V semiconductors) that could provide the optimum ON/OFF ratio as channel length is decreased.
1. Abstract Binary Switch Fig. 1a shows an abstract model for a binary switch whose state is represented by different positions of a charged material particle. The two requirements for the implementation of a particle-based binary switch are the ability to detect the presence/absence of the particle in e.g., the location x1, and the ability to move the particle from x0 to x1 and from x1 to x0 .
An elementary switching operation of a binary switch consists of three distinct phases. For example, consider the switch in Fig. 1a switching from "0" to "1". The three steps are: 1) the initial STORE "0" mode, 2) the transition CHANGE "0-1" mode, and 3) the final STORE "1" mode. All three modes have characteristic times determined by physics and can be described by the coordinate and velocity of the information carrier/material particle.
1
a
A
Eb L eVAB
B
b
A
eVAB L
B
Fig. 1. Fundamental operation of a binary switch: (a) STORE operation: the barrier height Eb is sufficient to prevent spontaneous transitions. An energy difference eVAB between the states A and B is needed to ensure particle transition from A to B and to enable detection of the particle's location (in digital application usually eVAB=Eb); (b) State CHANGE operation: the barrier height Eb is suppressed, while energy difference eVAB between the wells A and B is maintained.
The operation of the idealized switch can be described as follows: In STORE "0" the particle must be located in position x=x0 and remain there for the time Tstate, In CHANGE "0-1" mode, the state is undefined, as the particle is in the transition from x0 to x1 with a velocity v01>0 (for simplicity, we can take velocity to be the linear dimension of the switch divided by transition time). In STORE "1" ("0") the particle must be located in position x=x1 (x0) and have lifetime
state. The switching time tsw in this case is given by tsw=L/v01, where L=x1-x0 is the linear size of
the binary switch.
2
What are the requirements for state and tsw in a binary switch for information processing? Since binary logic operates with two logic states `0' and `1', while the binary switch has three physical states `0', `1' and UNDEFINED (i.e. CHANGE), if the READ operation of binary switch occurs in the UNDEFINED state, an error will result.
The conditions for maximum distinguishability of an ideal binary switch are:
max (i) Unlimited lifetime of each state in the absence of control signal: state in STORE
mode (for example, in synchronous circuits with clock, state [t clock , [ , where tclock is the clock period. (ii) Fast transition between binary states at the presence of control signal: tsw0 in CHANGE mode (say a negligible fraction of the clock period).
max Since state in STORE mode, the particle velocity in both 0 and 1 states must be zero, since
mv 2 the particle must be at rest, i.e., v0= v1=0, i. e., the kinetic energy E= of the particle should 2 ideally be zero in both STORE modes. In the CHANGE mode, the average particle velocity is
v01 > 0 � and E>0.
What are the requirements to Tstate and in a binary switch for information processing? Since the binary logic operates with two logic states `0' and `1', while the binary switch has three physical states `0', `1' and UNDEFINED (i.e. CHANGE), if the READ operation of binary switch in the UNDEFINED state occurs, an error will result. Thus the READ error probability is the probability that a binary switch at a given time is in the state UNDEFINED state is
3
err =
t sw store + t sw
(1)
and the probability to read a correct state is
correct = 1 - err =
store + t sw
store
=
Q , Q +1
(2)
Where Q is a measure "quality" of binary switches, Q =
store
tsw
. It is related to the probability of
correct operation and also is an indicator for the Ion/Ioff ratio of a charge-based device. We completely lose the distinguishability of the state when error probability is 50% or less and thus we set the upper boundary for err in a binary switch:
err < 1 2
(3)
Thus the lower boundary for Tstate can be obtained as:
tsw 1 < store > t sw store + t sw 2
(4a)
or, equivalently
Q >1
(4b)
Below we consider effects of particle mass on the `quality' of the binary switch. We will use an abstract device consisting of a single particle of mass m processing elementary charge e.
2. Switching and STORE time In CHANGE or switching phase (Fig. 1b) energy E=eVAB=Eb is supplied to the particle (eVAB=Eb in digital device applications),. For the simplest case of constant velocity, the switching time tsw can be estimated as
4
tsw =
L m =L . v01 2 Eb
(5)
The corresponding single-particle switching (`ON') current is
I on = e t sw
(6)
In STORE phase (Fig. 1a), the store time or time-to-error can be calculated as
err =
e I
(7)
where e is elementary charge, and I is the `barrier leakage' current (it can include over-barrier current due thermal excitations and tunneling current). For a single transmission channel the `leakage' (`OFF') current can be calculated from the Landauer formula [1]:
I off = 2e 2 2e V AB trans = E b trans h h
(8)
where trans is the transmission probability of the barrier. From (8) and (9), the time-to-error is:
err =
1 h 2 Eb trans
(9)
Two types of unintended barrier transitions can occur: "classical" and "quantum". The "classical" transmission occurs when the particle jumps over barrier. This can happen if the kinetic energy of the particle E is larger than Eb. The corresponding "classic" or Boltzmann transmission probability, B, is obtained from the Boltzmann distribution as:
B
E B = exp - b k T B
.
(10)
Another class of error transmissions, called "quantum errors", occur due to quantum mechanical tunneling through the barrier of finite width L. If the barrier is too narrow, spontaneous tunneling
5
through the barrier will destroy the binary information. The conditions for significant tunneling can be estimated using the Wentzel-Kramers-Brillouin(WKB) approximation [2]:
2 2m (11) WKB exp - L Eb h As follows from the above, here are two mechanisms of spontaneous transitions in binary switch:
the over-barrier transition and through-barrier tunneling. The joint error transmission probability of the two mechanisms is [3]:
trans = C + Q - C Q
(12)
Or, from (10) and (11), obtain: 2 2 Eb 2 2 Eb E E trans = exp - b + exp L m - exp - b exp - L m k T k T h h B B Now, the STORE time (or time-to-error), according to (5), (9) and (13) is: (13)
store
2 2 Eb 2 2 Eb E h Eb + exp - exp - L m - exp - b exp - L m (14) = k T 2 Eb k B T h h B
-1
3. The Q-factor of binary switch We can now express the `quality' of the switch Q as:
Q=
store
t sw
E exp - b = k T L 2 mE b B h
2 2Eb E + exp - L m - exp - b k T h B
2 2Eb exp - L m (15) h
-1
Electrons in solids are characterized by effective mass m*, which is in general different from the electron rest mass me. It is convenient to express m* in units me. Fig. 2 shows the function Q(m*) for L=100 nm, 30 nm, 10 nm and 5 nm.
6
Eb=0.75 eV; L=100 nm
6.00E+11 5.00E+11 4.00E+11 1.40E+12 1.20E+12 1.00E+12 8.00E+11
Eb=0.75 eV; L=30 nm
Q
3.00E+11 2.00E+11 1.00E+11 0.00E+00 0 0.2 0.4 m/me 0.6 0.8 1
Q
6.00E+11 4.00E+11 2.00E+11 0.00E+00 0 0.2 0.4 m/me 0.6 0.8 1
Eb=0.75 eV; L=10 nm
1.60E+12 1.40E+12 1.20E+12 1.00E+12 1.60E+12 1.40E+12 1.20E+12 1.00E+12
Eb=0.75 eV; L=5 nm
Q
8.00E+11 6.00E+11 4.00E+11 2.00E+11 0.00E+00 0 0.2 0.4 m/me 0.6 0.8 1
Q
8.00E+11 6.00E+11 4.00E+11 2.00E+11 0.00E+00 0 0.2 0.4 m/me 0.6 0.8 1
Fig. 2
The plots for L=100 nm (Fig. 2a) suggests that smaller mass is preferable for best performance of the binary switch. However, as L decreases, a maximum appears on the plot Q(m*), as shown in
* Fig. 2(b-d). The maximum corresponds to an optimum effective mass mopt of the information* bearing particle in the binary switch. For a given Eb, the optimum effective mass mopt increases
as L decreases.
* * Note that for m* < mopt the Q-factor degrades very rapidly, while at m* > mopt the function Q(m*)
decreases very slowly remaining of the same order of magnitude as Qmax within a large range of masses. If plotted in a logarithmic scale, Q(m*) has a plateau with a very small decline for
7
* masses greater than m* (Fig. 3). As follows from Fig. 3, for m* mopt (the plateau region) Q is * much greater then if m * < mopt . Thus the necessary condition for a high-Q binary switch is: * m* mopt
(16)
Eb=0.75 eV
1.00E+13 1.00E+12 1.00E+11 1.00E+10 1.00E+09 1.00E+08 L=10 nm L=5 nm L=3 nm 1.00E+07 1.00E+06 1.00E+05 1.00E+04 1.00E+03 1.00E+02 1.00E+01 1.00E+00 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
*
Q
m /me
Fig. 3
* To find mopt , we take the first derivative of (16). To do this, we use the following notations:
y=L m
=
h 2 Eb Eb k BT
= exp - =
2 2 Eb h
Eq. 15 then becomes: Q( y ) =
[ + e y
- y
- e - y
]
(17)
We look for a maximum of Q(y) by seeking (Q ( x ) ) = 0 .
8
Q( x ) = -
x
2
[ + e
- x
- e - x
]
-1
+
[ + e x
- x
- e - x
] (- e
-2
- x
+ e -x =0
)
(18)
After transformations, obtain:
(1 - y )e-y =
1-
(19) e obtain 1- (20)
Multiplying both parts of (16) by e=2.718...and using notations z=(1-y), =
ze- z =
The solution of (21) is
z = W ( )
(21)
where W() is the Lambert's W-function. Solutions of (17) and their implications for different generations of binary switches will be discussed in the next sections.
4. Semiconductor binary switch An example of a semiconductor binary switch is the field effect transistor (FET). Information� bearing particles in semiconductor devices are electrons with effective mass m*. Table 1 presents
* solutions of (18) for mopt at different L (the corresponding characteristic length in FET is the
gate length Lg). Table 1 contains semiconductor materials with effective electron mass close to
* * mopt and satisfies the condition m* mopt . The conditions for a suitable materials for a given Lg * are: m * mopt ( L g ) and E g E bmin . 2005 ITRS [4] projects EbL min 0.7eV based on thermal
noise and leakage considerations. Therefore in Table 1, some materials are marked as unsuitable for application in extremely scaled digital logic because Eg<0.7 eV.
9
Table 1. Semiconductors whose effective mass approximates the optimum effective mass for different for different FET gate lengths.
Semiconductor L=Lg, nm 30
* mopt / me
m*/me InSb InAs GaSb GaAs InP InN Ge Si GaP ? ? ? 0.01 0.02 0.04 0.06 0.08 0.11 0.12 0.26 0.35 ? ? ?
Eg, eV 0.17 0.35 0.73 1.42 1.34 1.97 0.66 1.12 2.26 ? ? ?
0.01
20
0.03
Suitability for FET channel No No Yes Yes Yes Yes No Yes Yes ? ? ?
Year of insertion
2009
10 9 8 7 6 5 4 3
0.12 0.14 0.18 0.24 0.32 0.47 0.73 1.30
2015 2016 2017 2018 2019 2020 ? ?
1.E+13 1.E+12 1.E+11 1.E+10 1.E+09 1.E+08 Q 1.E+07 1.E+06 1.E+05 1.E+04 1.E+03 1.E+02 1.E+01 1.E+00 1 10 Lg , nm 100 InAs GaSb GaAs InP Ge Si GaP
Fig. 4. A log-log plot of Q vs. gate length, Lg, for various semiconductors emphasizing Lg<10 nm regime
10
2.E+12 1.E+12 1.E+12 1.E+12 Q 8.E+11 6.E+11 4.E+11 2.E+11 0.E+00 0 10 20 30 Lg , nm 40 50 60
InAs GaSb GaAs InP Ge Si GaP
Fig. 5. A linear plot of Q vs. gate length, Lg, for various semiconductors, emphasizing Lg>10 nm regime
10
?
Eb=0.75 eV
1
m/m e
GaP
Si Ge GaAs InP GaSb InAs InSb
0.1
0.01
0.001 0 5 10 15 20 25 30 35 40 45 50
Lg, nm
Fig. 6. A plot showing gate lengths for which various semiconductors provide maximum Q.
11
Note from Fig. 4 that as gate lengths decrease below 10 nm, the Q-factor, for silicon degrades much more slowly than other semiconductors. For example, at Lg=7 nm, the Q for silicon is three orders of magnitude greater than the next closest semiconductor, germanium.
On the other hand, in Fig. 5, which is plotted on a linear scale, we see that the Q factor for silicon at 50 nm is about a factor of 5 inferior to the highest performance semiconductor, InSb.
In Fig. 6, we show the optimum effective mass as a function of gate length, annotated by the appropriate semiconductor material to achieve maximum Q. It is interesting that as gate length decrease, the best choice changes from the III-V semiconductors with lighter effective mass to silicon, which has higher effective mass for electrons.
5. Provisos The analysis and conclusions of this paper are based on the idealized abstract binary switch model. The basic assumptions were: 1) single-particle (e.g. single-electron) operation; 2) the binary states are separated by an ideal `sharp' barrier with abrupt walls, and barrier height independent on applied voltage, and 3) tunneling current was calculated assuming rectangular barrier of the height Eb and width L. Such idealizations results in largest possible Ion/Ioff ratios. The model can be extended to practical semiconductor devices by considering multi-electron operation and realistic barrier shapes. The latter include image force smothering of the barrier and finite spatial extension (barrier walls have a slope). As result, the effective barrier height will decrease when voltage is applied, and the over-barrier OFF current will increase (this is one manifestation the short-channel effect in semiconductor FET). Also, the effective barrier width
12
will decrease with applied voltage giving rise to the tunneling component of the OFF current. Thus the ON/OFF ratios in practical devices will be consistently less than in the abstract binary switch. Finally, we did not include the physics of barrier formation and control. For example, it was assumed that the height of the barrier formed between alternative channel semiconductor and the wells (i.e. source and drain) could be tuned to the required value (e.g. to ~0.7 eV). Moreover, the gate tunneling current, which results from the implementation of barrier control, was not included. A more detailed analysis would provide more accurate performance estimates for the switch.
6. Discussion There appears to be risk involved in developing technologies for alternative, e.g. III-V semiconductors, channel materials due to the relatively short interval of channel length over which a given material is optimum. In the regime 20 nm-5 nm, no material provides a performance advantage of more than approximately factor of two, and this advantage is shortlived as channel length is decreased. Silicon is the optimum material for the 7-10 nm region. GaP channel materials may, in principle, cover 6-10 nm region, however, the hypothetical benefits of GaP would also be short lived.
On the other hand III-V materials might offer an alternative route for device performance improvement independent from scaling for channel lengths that exceed about 20 nm. Such a strategy might buy time to allow for lithographic capability advances for use in the sub 20 nm channel length regime.
13
7. Conclusions and Future Studies One of interesting aspects of this study is the prescription for increased effective electron mass as gate length decreases. This has caused the authors to speculate that perhaps this is an indicator of a possible research direction for sub-5 nm devices. We plan to explore this question in a subsequent paper.
References 1. S. Datta, Electronic Transport in Mesoscopic Systems (Cambridge University Press, 1995) 2. A. P. French and E. F. Taylor, An Introduction to Quantum Physics (W. W. Norton & Co, Inc., 1978) 3. A. M. Yaglom and I. M. Yaglom, Probability and Information (D. Reidel, Boston, 1983). 4. ITRS, 2005: Semiconductor Industry Association (SIA), International Technology Roadmap for Semiconductors 2005 edition. Austin, TX: International SEMATECH
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