SEMATECH to Continue Pursuing Planar Transistor Scaling Strategy

 Dan McGowan
Austin, TX (5 February 2007) — Front-end engineers at SEMATECH will combine planar CMOS approaches with new channel materials to develop effective transistors for the 22 nm half-pitch technology generation – but will continue to investigate FinFET devices as an alternative approach.
This ongoing strategy has been solidified by inputs from the consortium’s member companies and from a select group of industry experts at a SEMATECH‑sponsored workshop held in conjunction with the recent International Electronic Devices Meeting (IEDM) in San Francisco, CA.
“It appears there is still enough life left in planar scaling for the nearer term, especially with the incorporation of Ge in to Si devices, but that three-dimensional devices and associated design capabilities will be needed to realize FinFET technology in the near future, ” said Raj Jammy, director of SEMATECH’s Front End Processes (FEP) Division.
The SEMATECH expert workshop,New Channel Materials Versus New Device Structures for Future MOSFET Technology,” consisted of two blue-ribbon panels representing planar CMOS and FinFET design advocates, with speakers offering viewpoints on the advantages and challenges of their respective technologies.
Panelists included Krishna Saraswat, Stanford University; Jerry Fossum and Scott Thompson, both of the University of Florida; Thomas Ernst, LETI; Leo Matthew, Freescale; Wilman Tsai, Intel; Judy Hoyt and Jesus del Alamo, both of MIT; Witek Maszara, AMD; and Wade Xiong, Texas Instruments. The panel discussions were preceded by an introduction by Ghavam Shahidi of IBM’s T. J. Watson Research Center.
Assessments from these and other technologists confirmed the current direction of FEP’s CMOS Extension Program, launched in early 2006. A key goal was to investigate strategies for planar CMOS scaling, including alternative materials to silicon in MOSFET channels, the critical pathways that permit faster transistors. The program also was charged with examining non-planar CMOS device structures, including double gate FinFETs and associated process development to improve their feasibility.
Hsing-Huang Tseng, chief technologist of FEP and program manager, explained that engineers have used “various tricks” to induce strain at the channel in an effort to improve mobility – but added that this approach alone may not be effective enough at the 22 nm half-pitch generation and beyond.
“New channel materials are the direction we want to go,” Tseng said, adding that options include silicon-germanium (Si-Ge), germanium (Ge), and more untested elementsin the III-V columns of the periodic table. SEMATECH is investigating several variations of this approach, such as using silicon or silicon-germanium for NMOS and Ge or Si-Ge for PMOS channels; or III-V materials on Si platform for NMOS in the near future. These materials would be applied as ultra-thin epitaxial layers grown selectively on Si to minimize defectivity.
“The idea of using two different materials in the channels for CMOS is relatively new, but is gaining momentum,” Tseng noted. Still, Tseng said serious challenges remain for extending the life of planar CMOS, such as the need to reduce defects in Ge or Si-Ge layers; ensuring that the mobility advantages observed for bulk materials are not lost when epitaxial channels are grown on Si; and control of Ge band-to-band tunneling, which increases overall leakage current.
Beyond the 22 nm generation, in addition to the efforts involving planar devices using new channel materials, SEMATECH will probe the usability of the FinFET, which can provide better short-channel control while offering greater speed. However, there appear to be too many unsolved manufacturing and design challenges to implementing these three-dimensional transistors with 22 nm device dimensions – leading the workshop panel to conclude that realization of FinFETs will require a serious effort now to develop the necessary design tools.
“Scaling CMOS technologies with new channel materials appears to have greater potential in the nearer term, but we will continue to pursue non-planar approaches for more distant technology generations,” said Jammy. “This is consistent with SEMATECH’s philosophy of extending incumbent technologies to the limit, while evaluating and narrowing options for promising future technologies.”
SEMATECH is the world’s catalyst for accelerating the commercialization of technology innovations into manufacturing solutions. By setting global direction, creating opportunities for flexible collaboration, and conducting strategic R&D, SEMATECH delivers significant leverage to our semiconductor and emerging technology partners. In short, we are accelerating the next technology revolution. For more information, please visit our website at SEMATECH, the SEMATECH logo, AMRC, Advanced Materials Research Center, ATDF, the ATDF logo, Advanced Technology Development Facility, ISMI and International SEMATECH Manufacturing Initiative are servicemarks of SEMATECH, Inc.
Domain: Electronics
Category: Semiconductors
Contact Person Address: SEMATECH
Posted By: Dan McGowan and Contact Dan McGowan
Semiconductor Analytics

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