Self-Aligned Double Patterning

 Applied Materials

Self-Aligned Double Patterning Seen as Cost-Effective Path to 32-22nm Scaling

With 32nm technologies ramping within the next two years, the extension of optical lithography to meet patterning requirements is the industry’s most urgent technology hurdle. After a recent day of technical discussions and presentations at the Sainte Claire hotel in San Jose, California, it looks like a technique called Self-Aligned Double Patterning (SADP) may be the most cost-effective answer to continued scaling down to the 22nm node.

During a panel discussion that included Jongwook Kye from AMD, Cheol Kyu Bok from Hynix, Mike Smayling from Tela Innovations and Ram Peltinov from Applied, a consensus was reached that extreme ultraviolet (EUV) lithography will eventually replace optical lithography. However, since EUV is not likely to be ready for mass production until 2012, optical lithography must soldier on to pattern 32nm and maybe even 22nm devices.

Immersion optical lithography has found rapid acceptance and most companies will use it at the 45nm node. Beyond 45nm, however, more advanced immersion fluids and lenses are necessary, but those developments will probably not be ready for the 32nm node. Double patterning (DP), a technique in which features are printed in two steps to double the pattern density, offers a solution. There are two main approaches to DP: double exposure (DEDP), which uses two masks, and self-aligned double patterning (SADP), also known as spacer-based patterning, which generates pairs of features from a single parent.

The most difficult challenge in DEDP is overlay control. The exact overlay specification is a matter for debate, but Dr. Cheol Bok of Hynix, speaking during the panel discussion, believes it must be as low as 1nm, much lower than the 5nm being currently demonstrated. This specification gap may prove difficult to close in time for 32nm.

One of the key advantages of SADP, in contrast, is that because all features come from a single exposure, the overlay error is greatly reduced. Anisul Khan of Applied reported that its advanced patterning films offer very low line-edge roughness and are tolerant of photoresist imperfections, often improving CD uniformity as the pattern is transferred into the underlying layers. In an earlier presentation, Chris Bencher, from Applied’s Maydan Technology Center, showed excellent 32nm and 22nm demonstration results in APF hardmask, TANOS, Cu-filled trench, oxide, STI and logic structures. Demonstrating the production-worthiness of SADP, Bencher said that at least one major memory manufacturer is using SADP in 45nm NAND flash memory production today.

SADP may be appropriate for regularly structured memory devices, but can it be extended to logic? Milind Weling from Cadence Design Systems explained that it is entirely feasible to alter the design rules for logic to produce flash-like structures. He demonstrated layout tools for automating the process. In addition, Tela Innovations has developed tools to redraw existing logic layouts to follow “gridded” design rules. Applied has validated this approach by fabricating demonstration logic structures using SADP.

Inevitably, the extra complexity of DP carries the risk of increased cost. How can these costs be offset and actually reduce the cost-per-chip, which is the most important metric? The answer lies in increased productivity in every area: denser features results in more chips per wafer; improvements in defect control, such as the introduction of “bevel engineering” will reduce defectivity and boost the number of good chips; and new factory automation software tools, such as Applied’s E3 APC application, increase output by raising overall fab productivity.
For additional information and photos concerning this news story, contact Connie Duncan at 408-563-6209.

Connie Duncan | Sr. Manager | Product Public Relations | Corporate Affairs | Applied Materials | 3050 Bowers Ave. | Santa Clara, CA 95054 |☎ 408.563.6209 |
Views: 3911
Domain: Electronics
Category: Semiconductors
02 September, 2008
02 September, 2008
02 September, 2007