Raj Jammy manages the front-end transistor program at Sematech which developed a high-k/metal gate solution for the member companies.
Jammy, on assignment to Sematech from IBM, answered questions about the consortium’s high-k effort.
Q. Do any of the smaller Sematech member companies primarily use the Sematech high k/metal gate solution, or do they all combine the Sematech information with their own ideas?
Jammy: The members extract it for their own purposes. At Sematech we screened more than 270 metal systems, including elemental, binary, and quaternary metals, in combination with dielectric combinations, mainly hafnium silicate and hafnium oxide dielectrics. We heated them up, and obtained the work functions for these metals. We also developed the process integration to develop a complete CMOS solution. We carefully document all the information, and provide it to the members through our formal tech transfer process.
Q. With the need for separate metals for the N- and PMOS, adding high-k sounds expensive. Is it?
Jammy: Each member company has their own business interests, with their own targets. Right now, adding high-k and metal gate is not cheap. It complicates the entire process. Today the industry uses a single conventional oxynitride, but at different thicknesses for different markets. The polysilicon electrodes require straightforward mask and implant steps.
Compared with that simple solution, high-k and metal gates are much more complicated. We process the NMOS metal and dielectric first, mask off the N side, go back and put down the P metal and dielectric. The additional complexity also has a yield impact that you have to be ready for.
However, one way to look at it is that with the dual stress liners for the N- and PMOS at the 90-, 65- and 45-nm generations, those dual stress liners meant that for the first time the N- and P-stack were done separately. Since the need to process N and P stacks separately is already there, high-k and metal gates are just adding to that complexity.
Q. Will high-k spread out to low-cost applications fairly quickly, or will it take five or ten years?
Jammy: My expectation is that companies offering real ultra-low power applications, where every bit of leakage matters, will apply high k/metal gate solutions as quickly as they can. Those volumes will help bring down the costs and make high-k easier to implement for other applications.
Q. Will some companies use ALD, and others MOCVD?
Jammy: At Sematech we have used ALD approaches. We simply have not worked enough on MOCVD for me to comment, honestly.
There are different issues for depositing the dielectric and the electrode. Some ALD is used for the metals, and some conventional PVD approaches can be used. It depends on what you are trying to accomplish.
Remember that MOCVD was optimized for depositions a few hundred angstroms thick, while ALD targeted a few tens of angstroms. The throughput of ALD is low but at the same time we are not depositing much, so the time in the chamber is relatively short and we can put more wafers through. ALD is at a relatively nascent stage of improvement compared with CVD and there is lots of room for improvement.
Right now our program is looking at how can we continue to scale these gate stacks and keep them cost effective, to make them multi-generational solutions so the same tools can be used. The thrust is to build on the incumbent high-k and metal gate technology and make it cost effective for the member companies.
Tomorrow: What high-k means for CMOS performance.