Technical Highlights for IEEE International Interconnect technology Conference

 Gary Dagastine
2007 IEEE International Interconnect Technology Conference (IITC) TIP Sheet, by Gary Dagastine, PR counsel to the conference
This Tipsheet, will give you an advance look at some of the papers to be given at the tenth annual IITC, to be held June 4-6, 2007 at
the Hyatt Regency San Francisco Airport Hotel. It will be preceded by a
Short Course on Sunday, June 3, taught by working experts in the field.
1. Highlights from the IITC Technical Program
Progress and Challenges in 3D Chips: There is much interest in 3D
architectures because their interconnects are potentially much shorter
than in traditional 2D configurations, allowing for higher system speed
and reduced power consumption. Other benefits may include less latency,
smaller form-factors, reduced cost and the ability to integrate
heterogeneous technologies. At IITC 2007, IMEC and Freescale
Semiconductor will present papers addressing practical issues related to
3-D circuits.
IMEC researchers will describe how they used copper-to-copper
thermocompression bonding with a spin-on compliant dielectric glue layer
to create 3D systems with improved thermal and mechanical stability.
The glue layer also allowed separate die-stacking and die-bonding
operations. This way, a landing wafer first can be populated with dice
in a fast pick-and-place operation, then the dice can be bonded
collectively later. The glue layer had no impact on the resistance of
through-wafer via-chain test structures (10µ pitch and 5µ diameters).
The thermocompression bonding is too time-consuming to be
production-worthy (>15 min./stack) but is promising. (Paper #11.3,
Simultaneous Cu-Cu and Compliant Dielectric Bonding for 3D Stacking of
ICs, A. Jourdain et al, IMEC)
Meanwhile, Freescale and Leti researchers will discuss the importance of
a cleanroom environment. They created 3D circuits using a
dielectric-to-dielectric direct wafer bonding process and 90nm low-k
interconnect technology. They will report that the quality of a direct
dielectric bond is strongly dependent on keeping the respective surfaces
clean, otherwise bubbles may form between the two wafers, especially
during CMP. (Paper #5.3, Three dimensional chip stacking using a
wafer-to-wafer integration, R. Chatterjee et al, Freescale
High-Performance Analog/RF: MIM (metal-insulator-metal) capacitors are
widely used in high-performance radio-frequency and analog applications.
STMicroelectronics will describe an innovative 3D MIM capacitor
structure embedded in a copper interconnect stack that enabled very high
capacitance densities (17 fF/µm2) without compromising the performance
of the dielectric. (Paper #8.2, Impact of TaN/Ta copper barrier on
full PEALD TiN/Ta2O5/TiN 3D damascene MIM capacitor performance, M.
Thomas et al, STMicroelectronics)
Chip-Package Interactions: NEC will discuss how packaging affects the
reliability of a chip's porous low-k SiCOH dielectric (k=2.9). Such
dielectric’s low mechanical strength and adhesion are stumbling blocks.
The team used two popular surface-mount chip packages (PBGAs and QFPs)
to identify a key issue: delamination between the low-k SiCOH dielectric
and the SiCN cap above it. The latter significantly impacts wire-bond
reliability, but spreading the contact area of the bonding wires seems
to reduce bonding failures. (Paper #9.5, 45nm-node Interconnects with
Porous SiOCH-Stacks, Tolerant of Low-Cost Packaging Applications, N.
Inoue et al, NEC)
Self-Formed Barriers and Hybrid Structures for 32 nm: Sony and Toshiba
will present papers discussing self-forming barrier layers integrated
with hybrid dual-dielectric structures for the 32-nm node. The hybrid
structures have one dielectric at the bottom of the via and a different
one on the top, to optimize performance and reliability. Self-forming
layers create both the barrier layer and the copper seed layer in one
step, reducing the complexity of the fabrication process. Also, the
barrier doesn't form at the bottom of vias, so via resistance is low,
and because these layers are very thin there is more copper in the
trenches, and thus the resistance of the copper lines is less.
Sony researchers will describe an architecture composed of a Cu ultra
low-k SiOC (k=2) interconnect and an SiOC (k=2.65) hard mask structure.
It demonstrated excellent stress-induced voiding performance, long
electromigration lifetimes and it didn't require pore-sealing. (Paper
#4.5, Integration of High Performance and Low Cost Cu/Ultra Low-k
SiOC(k=2.0) Interconnects with Self-formed Barrier Technology for 32
nm-node and Beyond, Y. Ohoka et al, Sony)
Toshiba researchers will describe a porous SiOC/porous-PAr (k=2.3)
hybrid dielectric combined with a copper-manganese alloy seed. (Paper
#2.3, Self-Formed Barrier Technology using CuMn Alloy Seed for Copper
Dual-Damascene Interconnect with porous-SiOC/ porous-PAr Hybrid
Dielectric, T. Watanabe et al, Toshiba)
Two-Level Simultaneous Air Gaps: Air has the lowest permittivity and
much work has gone into trying to create air gaps between copper lines.
An NXP Semiconductors team will describe an approach that minimizes the
cost, complexity and problems normally associated with multi-level air
gap schemes. Instead of creating air gaps by etching away material,
they used a spin-on thermally sacrificial polymer which leaves air gaps
behind as it degrades. They also used a SiOC CVD hard mask. Sacrificial
polymers have been used before, but this one is more rigid and led to
better trench profiles. By decomposing it on two different levels
simultaneously, the researchers created air gaps at two metal levels in
a 45-nm CMOS process. A resistance of just 2 ohms/via for 100-nm-wide
vias was measured. Much work needs to be done to perfect the technique,
but the work is a step toward making the technique practical. The
researchers say it is extendable to the 32-nm and 22-nm nodes, where
having air gaps also may help alleviate thermal issues. (Paper #4.3,
Multi-Level Air Gap Integration for 32/22nm nodes using a Spin-on
Thermal Degradable Polymer and a SiOC CVD Hard Mask, R. Daamen et al,
NXP Semiconductors)
Better Ruthenium Liner: Tantalum (Ta) and tantalum nitride (TaN) are
used as the barrier layer, or liner, between copper lines and the
dielectric. But copper can't be plated directly onto them, and it is
difficult to fill high aspect-ratio structures with them using typical
physical-vapor-deposition (PVD) processes. If ruthenium (Ru) replaces
the Ta layer, copper can be electroplated directly onto the Ru, and
ruthenium has lower electrical resistance as well. At IITC 2006, IBM
described a ruthenium-based barrier layer. This year, an NEC team will
detail how they've moved the technology closer toward practicality.
Using Ru barrier layers, a porous SiOCH dielectric (k=2.55) and PVD,
they achieved a 12.4% decrease in resistivity in copper lines. Matching
the orientation of both the ruthenium and copper grain structures
reduces electron scattering, and therefore resistance. (Paper #2.2,
Highly-oriented PVD Ruthenium Liner for Low-resistance Direct-plated Cu
Interconnects, M. Abe, NEC)
Electroplated Rhodium: An IBM team will describe a promising rhodium
(Rh) electroplating technology for contact plugs at the 32-nm technology
node. Rhodium is highly conformal, can be electroplated and doesn’t
require CVD-based fabrication, thus it can be used to fill very high
aspect-ratio vias (40nm x 240nm) with few defects. It is
corrosion-resistant, has low contact resistance and lower resistivity
than either tungsten, which was previously used in vias, or copper (with
Ti/Ru liners). The researchers say the possibility to use even thinner
layers of rhodium extends its potential use to future CMOS technology
generations. (Paper #6.4, An alternative low resistance MOL technology
with electroplated rhodium as contact plugs for 32nm CMOS and beyond,
I. Shao et al, IBM)
Three High-Speed Interconnect Options: Future high-performance computers
may require the integration of diverse interconnect technologies. Sun
Microsystems researchers will describe a 90-nm test chip they made which
integrated three types of chip-to-chip interconnects: capacitive
interconnects for proximity communication, optical interconnects
employing external lasers and photodiodes, and electrical interconnects
using current-model logic (CML) for high-speed operation and optical
compatibility. They will address interface requirements, chip layout
considerations and test results for each interconnect modality. They
verified interoperability between all three interfaces at speeds
exceeding 2.5 Gbps, and say the chip will enable future prototypes to
more fully characterize metrics such as power and latency, to further
explore die packaging, and to drive more aggressive interconnects such
as silicon-based photonics. (Paper #5.2, CMOS Integration of
Capacitive, Optical, and Electrical Interconnects, J. Lexau et al, Sun
Carbon Nanotubes Go Ballistic? At tiny dimensions, copper tends to
physically move with current flowing through it, leading to gaps or
outright breaks in the line. Carbon nanotubes (CNTs) aren’t subject to
this electromigration, and over the past several years attempts have
been made to replace the copper used in vias with bundles of nanotubes.
But this is difficult to do. At IITC, a MIRAI-Selete team will tell how
they grew a forest of carbon nanotubes not just in the vias but all over
the substrate's surface. Then, they planarized the surface with CMP.
Only the nanotubes that were in the vias remained. Their analysis
indicated current may flow through nanotubes by means of ballistic
transport, meaning that electron-scattering caused by defects or
impurities in the nanotubes is negligible. If true, this implies that
the electrical resistance of vias could be dramatically reduced by using
carbon nanotubes. (Paper #11.2, Electrical Properties of Carbon
Nanotube Via Interconnects Fabricated by Novel Damascene Process,, M.
Nihei et al, MIRAI-Selete)
How To Make Dense Bundles of Nanotubes: Another nanotube paper will deal
with how to make the carbon nanotube bundles denser in order to reduce
their resistance. To date it has proven impossible to grow closely
packed CNT bundles. A team from Rensselaer Polytechnic Institute
decided instead to focus on densifying the bundles once they were grown.
At IITC, the team will report how they immersed CVD-grown vertically
oriented CNTs in an organic solvent. When the solvent evaporated, the
individual nanotubes aggregated into higher-density bundles by capillary
coalescence. Their density increased from five to 25 times, depending
on bundle height, diameter, pitch, and specific CNT properties. (Paper
#11.1, Densification of Carbon Nanotube Bundles for Interconnect
Application, Z. Liu et al, RPI)
Big Results from Nano Clusters: The effective performance of
multi-layer dielectric stacks is worse than the theoretical k-value of
the dielectric alone would suggest. To bring the net
resistive-capacitive delay closer to the dielectric's theoretical
performance, Fujitsu researchers experimented with 45-nm six-level
interconnects using nano-clustering silica (NCS) as the dielectric
(k=2.25). By using NCS and also by thinning the barrier layer within
the trenches, they achieved as much as an 86-percent reduction in R-C
delays versus what the ITRS roadmap sets forth as a goal for 45-nm
technology. The resistance of the stacks did not increase even after
extensive thermal stressing, and the time-dependent breakdown of the
system, a measure of robustness, showed a life expectancy of 10 years.
(Paper #9.4, Strategies of RC Delay Reduction in 45 nm BEOL
Technology, H. Kudo et al, Fujitsu)
Riding the Wave: The timing of a chip’s internal operations is critical,
as one transistor’s output is another’s input and they must be
synchronized. But as chips grow denser, it’s harder to design and
verify these interactions, in large part because of growing
resistive-capacitive delays in the interconnect stack. Low-resistivity
metal, low-k dielectrics, 3-D integration and optical interconnects are
all potential solutions, but a Tokyo Institute of Technology team has
taken a completely different approach. They built a so-called
transmission-line interconnect architecture that transfers signal not as
current but as an electromagnetic wave, using on-chip inductors as
transceivers. Unlike previous on-chip signal-transmission schemes that
waste large amounts of static power, their low-voltage system does not.
They built it using a 90-nm silicon CMOS process, and demonstrated
10-Gbps signal transmission with only 2.7-mW power consumption. Delays
were as much as 89% less than with a conventional interconnect stack.
(Paper #10.3, A Low-Latency and High-Power-Efficient On-Chip LVDS
Transmission Line Interconnect for an RC Interconnect Alternative, H.
Ito et al, Tokyo Institute of Technology)
Conclusion: “Over the last ten years the semiconductor industry has made major improvements in interconnects to keep increasing device performance,” said Dr. Michael Shapiro, IITC 2007 Publicity Chairman and Senior Technical Staff Member and Emerging Technology Advocate, IBM Systems and Technology Group. “For performance improvements to continue, the next ten years will require constant advancement of the chip wiring. IITC presenters and attendees come from around the world to share knowledge that will determine the interconnect technologies of the future.”
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Domain: Electronics
Category: Semiconductors

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