Texas Instruments executives explained their plans for digital CMOS process technology development in some detail this week at the company’s annual financial analysts meeting in Dallas, following the company's January announcement that TI would turn over basic process technology development to foundry partners starting at the 32-nm node.
TI has committed to working with both UMC and TSMC for process technology development. In the second half of this year, it will decide on a third partner, with China’s SMIC and others on the list of candidates.
Kevin Ritchie, senior vice president of manufacturing, said “the foundries have closed the technology gap.”
Avoiding duplication of efforts is a prime goal of the switch, he said. “We all use the same tools, and we all get those tools at the same time,” he said, mentioning the leading suppliers of lithography, track, deposition, and etch tools.
Much of the process differentiation is bounded by the capabilities of the tools themselves.
“Now, we put a team together to learn how to etch a 32-nm line. The foundries put together their teams, and we all learn to do the same thing at the same time. It is repetitive work. We want to push our R&D dollars to where we can differentiate,” he said.
Going forward, TI will continue to work with Sun Microsystems to make its Sparc processors, with the TI team has been particularly involved in test, packaging, and technology definition. The wafers will run at UMC, where TI has been the largest customer for several years.
“We’ll continue to have the same production engineering team in Houston that has worked successfully to keep Sun on the leading edge for the past 20 years,” Ritchie said.
TI is reducing its digital CMOS development team from about 400 people to “more than 200 people doing CMOS development. It is not like we are going down to a handful. We will have 200 plus people here and in Taiwan doing process definition and process development. With the size of our team, I believe we can stay current,” Ritchie said.
By reducing digital CMOS development, TI will be able to transfer people to analog process development. TI now has four different analog flows to support D/A converters, power management, and other analog product lines.
For 45-nm technology, TI will continue to jointly develop process technology with its main foundry partners, running development wafers at the DMOS 6 fab in Dallas. Starting at the 32-nm node, those development wafers will run through fabs at UMC and TSMC.
“In the past, we had parallel efforts, independent paths. In the future, we will tell our foundry partners our specs, such as leakage and SRAM cell definition. Then we will copy those foundry processes back to DMOS 6 and the (yet to be equipped) R-fab. It will be a copy-exact process back to our fabs,” Ritchie said.
In recent years, TI has moved six or seven employees to Taiwan to work with its foundry partners there. That number will increase substantially as TI “shares its IP and trade secrets” with its partners.
Asked about the cost of developing a new process flow, Ritchie said just the capital equipment costs are in the range of $180-250 million, dominated by lithography tools that he said cost $30-50 million each.
“This has been a very difficult time for our people. We had one department-wide meeting, with (CEO) Rich Templeton in attendance. One employee who has been in silicon technology development for more than 20 years stood up to talk. He was choking back tears when he said ‘I believe this is the right decision for TI, but it hurts. He expressed the sentiments of all of us. There are a lot of people who have spent 25 or 30 years in silicon technology development at TI. They are very proud of their independence, and now we have a lot of rebuilding to do,” Ritchie said.
Next: TI's analog process plans