Wringing higher performance from CMOS transistors has become more difficult as scaling proceeds. So when TSMC first announced its 45-nm technology on April 9th, it wasn’t completely clear how the foundry would achieve its performance claims for its 45-nm high-performance technology.
Without introducing a high-k/metal gate solution, it claimed improvements which went beyond Intel’s claim of a 20 percent performance boost for its 45-nm process compared with the earlier generation.
Also, TSMC said the gate density of its 45 GS (General Superb, a new name for the high performance process) would be 2.35 times the gate density of the 65-nm GP transistor, instead of the normal density doubling.
The speed was said to be 1.39 times faster than the company’s 65-nm LP (low power) transistor, and the 0.9 V operating voltage was a marked improvement over the 1.1 V transistor at the 65-nm generation. That voltage improvement also was noteworthy, as high-performance processes from IBM and Intel will remain at 1 V operation at the 45-nm generation, despite strenuous efforts to go lower.
At the TSMC technology symposium in Austin Monday (April 16), TSMC managers explained that the high-performance 45 GS actually is based on 40-nm design rules. With risk production of the 45-nm LP starting in September 2007 and early production of the GS process beginning in May 2008, the company has time to shrink by about 10 percent and meet the tighter, 40-nm design rules, they said. (It raises the question whey TSMC doesn’t call it the 40 GS instead of the 45 GS.)
While few hard metrics were offered in terms of drive current or power consumption (the company offers comparisons between its own transistors/test circuits at the 65- and 45-nm nodes), the SRAM cell size was quantified at 0.242 square microns for the 45 GS process. Going beyond the 2X density increase normally expected from one node to another was emphasized Monday as a major technology advantage by the TSMC managers, who exhorted customers to begin 45-nm designs now so they would be ready for the cost/performance crossover which they said is coming as soon as the second half of next year.
One of the first companies on board the TSMC 45-nm process train is Qualcomm, which expects to begin 45-nm production by the end of this year. With immersion lithography used for many levels of the 45-nm process, the biggest concern is additional defect densities from the interaction of water and photoresists. TSMC officials insist that defects from immersion are well under control, with “proprietary” defect control techniques developed in Hsinchu which not even ASML is privy to, they said.
Immersion will be used widely in the 45-nm process. The 45-nm, 32-Mbit SRAM which TSMC demonstrated on Dec. 5, 2006 used immersion for “12-18 layers,” a TSMC manager said.
With 0.9 V operation, a 2.35-times gate density increase, and claims of a 40 percent speed improvement and a 45 percent active power savings, TSMC is making big claims for its 45-nm GS process. It will be interesting to see if these claims hold up next year, and if yields suffer, or not, from immersion’s introduction to a foundry’s premier process.