weVISION: The state of process development at Intel - 32nm, 22nm, 15nm, defect densities, Hi-K, Strained Silicon and billions of transistors . . . with Mark Bohr (video)
Posted on: 08-Mar-2009
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This video starts with a discussion of how Intelís 45nm production ramp going with a series of slides. Defect densities are the lowest for any Intel technology ever. Mark then discusses Intelís 32nm process including Defect Density trends, lithographic and lead and halogen free packaging challenges, interesting surprises with Westmere chips. It concludes with 22nm, 15nm, and Intel's efforts to develop new SoC process flows.
weQuest's are written by G Dan Hutcheson, his career spans more than thirty years, in which he became a well-known as a visionary for helping companies make businesses out of technology. This includes hundreds of successful programs involving product development, positioning, and launch in Semiconductor, Technology, Medicine, Energy, Business, High Tech, Enviorntment, Electronics, healthcare and Business devisions.