Dimitri Antoniadis, the Ray & Maria Stata Professor of Electrical Engineering at the Massachusetts Institute of Technology, fielded our questions about the high-k/metal gate topic from Singapore, where he is a visiting professor.
WeSRCH: High-k was a long research effort. What were some of the challenges?
Antoniadis: Early on, there was a significant reduction in the transport characteristics, the mobility. At one point people thought mobility was a fundamental issue, caused by phonon scattering in the high-k. But researchers added a little bit of oxide at the interface, and made other changes in the high-k itself. There were lots of processing tricks that ameliorated those issues. Reliability was a big issue. Finding the right metals, particularly for the PMOS electrode, with the right work functions, was a challenge. The overall process integration, with the dual metals, required a lot of work to put it all together. Getting to this point is a major milestone.
WeSRCH: How does a high-k and metal gate solution impact density? Can we shrink the transistors more easily because of high-k?
Antoniadis: Density will benefit, though I have no idea how it will impact Intel or IBM. The pitch is controlled by many things, the spacers, the size of contact, and so on. There was some leeway in staying on track with the pitch without scaling the gate length. In principle, if we have a lower effective oxide thickness (EOT), then we can reasonably scale the gate length. It is not exactly a 1:1 relationship, though. One reason we got stuck in scaling the gate length is that electrostatic integrity becomes compromised when we are not able to scale the oxide thickness. Scaling the gate oxide thickness opens up the path for continued gate length scaling.
WeSRCH: What should the EOT be for the 45-nm node?
The enhancement should be about 20-30 percent compared to the 65-nm node to be reasonably symmetrical. Before high-k, performance scaling was slowing down. At the 65-nm node we had only a 5 percent enhancement of the oxide inversion thickness, which includes a lot of things beyond the EOT. Ideally in terms of EOT, we would want to be in the range of 1 nm to 1.05 nm. The EOT at 65-nm was 1.2 nm, roughly, for high performance devices. So nominally would want a 20 percent to 30 percent decrease in the EOT, which should go as the gate length. The gate length, in principle, scales 30 percent per generation. Intel is talking about a 20 percent performance enhancement at the 45-nm generation, but I am guessing that that is the improvement in the oxide thickness lumped together with strain and other techniques. Shaving the oxide thickness from about 1.2 to 1 – if that is in fact what they can do – is a very good step.
WeSRCH: Why does a thinner oxide improve the switching speed?
Antoniadis: There are two ways to think of performance. When the transistor is driving a fixed capacitive load, the switching time is faster the more current is being driven. The current depends more or less linearly on the capacitance, which is an inverse relationship to the thickness of the oxide.
Another way to think about it is to think about the switching time for a fixed load. Everything else being the same, the thinner the oxide, the faster the switching of a fixed load would be. It is not exactly that simple because in a chip the load is produced by other transistors as well as interconnect lines. In reality that doesn’t translate into speed one-to-one, but the trend is in the right direction. If you put it all together it results in an increase (in performance). Because of a decrease in the oxide thickness, we can also decrease the gate length. Decreasing the oxide thickness in the past has allowed performance to scale linearly with pitch. Of course, the devil is in the details, and we will have to wait and see Intel’s transistor characteristics, to see what their exact performance is. But it sounds very good.
WeSRCH: What about leakage?
Antoniadis: There are two kinds of leakage. One is channel leakage, where the current conducts in the off-state through the channel, or what we call the Ioff
state. Then there is gate leakage, in which current leaks through the gate to the S-D, in the on state. It occurs mostly when the chip is in the on state but not conducting, after the transistor has done its job discharging the capacitor, when the gate is at high potential and everything else is low. That is when it leaks the worst.
There is leakage through the gate to the channel when the device is off. What high k does immediately attacks the gate leakage…that is the big deal. It allows you to make an effectively thinner, lower EOT, without increasing the leakage. Decoupling the gate leakage from the EOT frees the hands of the device designer to use a lower EOT.
The drive current that companies want, at a small gate length, always must be viewed against the current leakage in the off state. Oxide thickness plays a role there. According to the scaling theory of (IBM research staff member Bob) Dennard in 1974, everything about the device must scale at the same time.
Considering the off current of the device, when the Ioff increases as we scale the gate length without scaling EOT, the electrostatics of the transistor is compromised. There is a minimum ratio before device stops being well-tempered. There is a minimum ratio. Once we can decrease the oxide thickness, we can decrease the gate length at the same leakage.
And I should add that it is not just changing the oxide thickness, we have to change the dopants in order to improve the off current and the leakage current when the device is on.
What Intel is saying is that at the same Ioff, they have a 20 percent performance enhancement. Or, if I keep the same Ion, I can have an Ioff that is four or five times less.