Share  Email

SPIE zeroes in on EUV lithography development

Posted on: 08-Feb-2007

Page Views: 2182

Now that high-k dielectrics are underway, we can shift our professional anxieties to extreme ultraviolet lithography.
EUV is entering a development phase that must make rapid progress, because the technical challenges facing EUV are, well, extreme. EUV started out as “soft X-ray” lithography back in 1988 when researchers from Lincoln Labs and Bell Labs began writing about the approach. The Berkeley, Livermore, and Sandia national labs teamed up with Intel and several other chip manufacturers to create a test system in 2000.
Intel has had one of the EUV micro exposure tools (METs) for several years in Hillsboro, Oregon. Late in 2006, both the IMEC and Albany Nanotech consortia received full-field alpha demonstration tools from ASML. Those alpha tools can create 40-nm lines and spaces, at roughly 10 wafers per hour throughput.
At the SPIE Advanced Lithography conference starting Feb. 26 in San Jose, ASML’s Noreen Harned will discuss EUV’s status and challenges. Engineers from Nikon and Canon will provide updates on those companies’ EUV development programs.
Tokyo has a major interest in EUV. Japanese engineers working at the government-funded Association of Super-Advanced Electronics Technologies (ASET) have several EUV papers on the program, ranging from new methods to keep the mirrors clean to refining the EUV photoresists. Japan’s EUV-specific consortium, the Extreme Ultraviolet Lithography System Development Association, will present progress on source development efforts.
European efforts include source work from XTREME technologies GmbH (Germany) and Philips’ German subsidiary. Cymer (San Diego) will update its source development efforts at SPIE.
EUV is at the stage where companies and consortia are running wafers and doing early manufacturability assessments. Engineers based at Albany, N.Y. from AMD, IBM, Micron, Qimonda, and the University of Albany, will present their early efforts at establishing an EUV baseline process. Intel engineers have a poster paper on their EUV process window study, and another Intel poster will present work on EUV flare and mean-time-between-failure measurements on the Intel micro-exposure tool.
It’s a field with plenty of time pressure: memory and MPU companies need high- throughput EUV systems for the 22-nm node, beginning just four years from now.

« Freescale out, Panasonic in, at Sematech

Intel teraflops processor calls out for apps »

About weQuest:
weQuest's are written by G Dan Hutcheson, his career spans more than thirty years, in which he became a well-known as a visionary for helping companies make businesses out of technology. This includes hundreds of successful programs involving product development, positioning, and launch in Semiconductor, Technology, Medicine, Energy, Business, High Tech, Enviorntment, Electronics, healthcare and Business devisions.

Short URL:

Send to Colleague | Send to myContacts |  Save to myLibrary