Share  Email

Intel teraflops processor calls out for apps

Posted on: 12-Feb-2007

Page Views: 1677

Intel’s 80-core teraflops processor, announced at the International Solid State Circuits Conference (ISSCC), is research-level hardware that points to major software efforts by the processor giant. Justin Rattner, senior Intel fellow, calls the research chip the first programmable teraflops processor, and he is is forthright that putting all those flops to practical use is the real challenge.
Intel is “working with end users to understand what applications are possible” with tiled processors. Intel calls the the overall field recognition, mining, and synthesis, he said.
“There are underlying algorithmic techniques which are common to e-learning, virtual travel, media content creation, business management. We see enormous applications in the health space, for example teams of surgeons doing virtual surgery, empowered by terascale technology,” Rattner said.
“We are very mindful of the programming challenges these chips pose, and we are making good progress. We have published papers on speculative multi-threading and transactional memory, on programming languages and compiler memory,” he said.
The chip features an 8-by-10 tile layout. Each tile includes a processing element with a routing element. The tiles have five I/O paths to connect to four adjacent neighbors, and to the vertically connected 3D SRAM array built below the processor elements.
The design uses a “mesochrynous” clocking scheme which saves power compared with a single clock unit. “In a traditional design, clocking take 30 percent. With this teraflops chip we are below 10 percent,” said Intel researcher Nitin Borkar. The clock skew between the individual tiles is small enough to ignore. Instead, the clocking scheme deals with accumulated skew across the die.
Power is conserved further by putting the data and instruction memory into sleep mode, and the router logic into quiescent mode. The chip has external voltage and frequency controls. The overall result is an energy efficiency of 16 GFlops-per-Watt, which Rattner said is the best reported to date.
While the chip consumes only 62 Watts in teraflops mode, it has a wide operating range. At 5.7 GHz, the upper end of the operating range, it is rated at 1.8 teraflops, though at that speed it consumes 260 Watts.

« SPIE zeroes in on EUV lithography development

Intel's teraflops processor points to 3D memo... »

About weQuest:
weQuest's are written by G Dan Hutcheson, his career spans more than thirty years, in which he became a well-known as a visionary for helping companies make businesses out of technology. This includes hundreds of successful programs involving product development, positioning, and launch in Semiconductor, Technology, Medicine, Energy, Business, High Tech, Enviorntment, Electronics, healthcare and Business devisions.

Short URL:

Send to Colleague | Send to myContacts |  Save to myLibrary