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Tezzaron readying MPW run for 3D memory/logic designs

Posted on: 21-Feb-2007

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Tezzaron Semiconductor (Naperville, Ill.), one of the pioneers of 3D interconnect technology, is putting together a Multi-Project Wafer (MPW) run. With large companies such as IBM, Intel, and Samsung working hard on 3D interconnects now, the MPW run provides an opportunity for companies of all sizes to get in on the 3D action and optimize memory bandwidth.
Bob Patti, the chief technology office at Tezzaron, said the effort is based on the company’s “Octopus” design, which positions layers of DRAM memory (512 Mbits per layer) on top of a memory controller layer. The memory is designed to be stacked onto a customer’s logic device. The Octopus handles up to eight data ports, each with a 128-bit bus in both directions, at a rate of 4 giga-transfers per second and a latency of 8 ns.
Patti said Tezzaron will customize its Octopus controller to integrate with each client’s proprietary device, and then build Octopus chips using its own wafer-on-wafer stacking capability. Clients will provide wafers containing their own devices; Octopus chips will be attached to these wafers using a die-on-wafer process.
“There is a lot of work required to get the appropriate mating of the two parts (the Tezzaron part and the customer’s). It often involves a custom package where the balls are moved around,” he said.
With that design work underway, the MPW tape-out is projected for the fourth quarter, with initial Octopus-on-device assemblies expected by late in the first quarter of 2008. Some clients are expected to step up to full production by the end of next year.
“The MPW provides up to eight clients a stepping-stone toward full 3D production at a significantly reduced cost,” Patti said. The initial MPW uses two-layer (512 Mb) Octopus parts – one layer of memory plus the controller. Clients can later request larger Octopus memories with three or five layers (1 and 2 Gbits respectively).
Meanwhile, Tezzaron is nearing completion on memory chips using its 3T-iRAM technology. This design will be sold as 72-Mbit single-layer devices as well as larger 3D stacked memories. The result, Patti said, is SRAM-like speeds, much-improved repair and redundancy, with industry standard packages and interfaces.
Tezzaron also is designing stand-alone stacked DRAM parts with built-in ECC.


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