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Stork at SPIE: voltage, interconnect, variability growing challenges

Posted on: 27-Feb-2007

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Lithography is only one challenge facing the semiconductor roadmap -- voltage scaling, interconnects, and local transistor variability are equally daunting issues, said Hans Stork, the director of silicon development at Texas Instruments.
Speaking to the plenary session of the SPIE Advanced Lithography conference in San Jose, Stork laid out the wider challenge: as video becomes more important on handsets, mobile devices need gigahertz-level performance as well as 240-hours-plus of standby time. However, the industry will need breakthroughs to boost performance and keep power consumption at bay, partly because operating voltages “are saturating at 1V,” Stork said. The silicon bandgap makes it difficult to go lower, and SRAM failures at sub-1V operation escalate quickly.
Local variability – in which one transistor differs markedly from the transistor next to it – is a growing challenge for circuit designers, one that “can be analyzed and predicted in principle” but is difficult to solve in reality. “Local exceeds global (variability), and that is a new phenomenon. Simulations do not take local variations into account,” he told several thousand engineers in the audience.
Interconnect scaling also has slowed down. “For ten years now we have been trying to get below an effective k-value of 3.5, and we are not making much progress.” When the vias and interconnect trenches are factored in, along with the etch stop and barrier layers, interconnects “have a huge impact on capacitance.” As copper lines shrink to nanometer dimensions, the increasing resistance of copper, particularly grain-boundary and sidewall-scattering issues, make it difficult to improve interconnect performance.
“We expect a 20 percent performance boost in CMOS at each generation, but when you can’t improve the interconnects that makes it more difficult to achieve those 20 percent gains,” he said.
Density scaling also is under pressure.
Strained silicon has helped the industry boost CMOS performance, but the deposited SiGe at the source and drain, and wider spacings, has had a density impact. Stork showed images of circuits with and without strained silicon, boosting the size of the strained-silicon-enhanced circuit significantly.
In order to double the number of chips on a wafer with each succeeding process generation, strained silicon’s impact and design rule restrictions make the challenge that much harder, he said.
Design rule restrictions are becoming more onerous. As lithography runs up against resolution limits, design teams are being told to limit themselves as much as possible to vertical and horizontal lines at fixed pitches, with squared contacts. “Allowing the pattern to happen in a predictable way affects our ability to shrink. We can handle that with standard cells that optimize the area while taking the patternability tradeoffs into account,” he said.
Lithographic double patterning adds to the modeling challenge as well, tripling simulation complexity. While EDA tools can use model-based techniques, “if there is no translation for the designers to understand and work with, it is not very practical. We need a balance between model and rule-based design,” Stork said.
And all of these technical challenges occur under an umbrella of tightening cost pressure. “I am putting a caution out there that the dynamics of the industry favor volumes and low costs,” he said.

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