This is the second part of an interview with Sitaram Arkalgud, director of Sematech’s 3D Interconnect program.
Q. Have you ranked the challenges to the through-silicon via approach?
Arkalgud: On the technical side, one of the biggest challenges is finding a cost effective manufacturing method. There are several different ways to go about it: companies could create the vias very early in the process and fill them with polysilicon – that is an approach some of the Japanese companies have been taking. Or you could do it a little bit later and fill them with tungsten. Or you could do it later and fill them with copper.
Then companies can bond the two die in different ways, using face-to-face bonding, or a back-to-face bonding. There are several permutations and combinations, and companies have to find one or two that make sense from a cost point of view.
Q. What about the equipment?
Arkalgud: Yes, another challenge is the infrastructure. For wafer-to-wafer approaches, how do you handle a stack of wafers? We have to work down to the level of the robots and alignment.
Now we have ad hoc applications, so we need to take those and make the process more systematic. To do that we need to pull in all the different parts of the industry.
Q. Are there standards needed?
Arkalgud: Like the JEDEC wiring standard, we will need a via-out standard. That way, companies could take chips from supplier A, B, or C, and have a standard way to stack them together, to mix and match the different elements. That kind of infrastructure is not there today.
How does the design flow go? What is the testing methodology?
Another challenge is that different companies have different needs, depending on whether the company is a logic, dram-flash, or analog vendor.
Q. Is the time for this technology getting closer?
Arkalgud: In the last few years at the Sematech interconnect program we were looking at what happens next, and certainly there are copper and low-k challenges. But that becomes very proprietary for big companies.
What comes after that? The Next Big Thing is good for a consortium approach, where the industry needs a broad program like this 3D interconnect program. Once you do something like this, for example, companies can do optoelectronics, using chip-to-chip interconnects. After that, we go on to MEMS, and then go on to connecting to biochips. Once you have the cost model down, then companies can put diverse pieces together.
Q. What about getting the heat out?
Arkalgud: These are solvable problems if people get their minds together and work on them. There is no doubt that heat is one of the biggest issues. In fact, once you start digging we uncover technical issues one after another. Heat is one of them. But there are proposals out there. A simple way is to put the hottest layer at the top or bottom of the stack and then heat sink it away. People have proposed using dummy copper vias which act as heat sinks, to bring the heat to the top or bottom and then wick it away.
If the industry had sophisticated design tools, we could place the hottest circuits where it makes sense so you can take the heat out.
We know everyone would like to have a (thermal) model. We could provide some of the thermal analysis tools to enable this approach.
Any other challenges?
Arkalgud: Alignment accuracy, which has implications on design and layout. We can have very high alignment accuracy, but then the throughput could be fairly slow. If we are doing a die-to-wafer approach, we are picking and placing a known good die on top of another level of known good die. That impacts the space around the vias, to account for alignment tolerance.
We strongly think the assembly side and the front-end wafer fab need to work much more closely together.
What about a roadmap?
Arkalgud: We are trying to get a through-silicon via roadmap in the 2007 ITRS. Then for the 2009 roadmap there could be a much broader 3D roadmap, including detailed via dimensions, and when we expect them to be there.
At Sematech, cost modeling is another big effort. We believe we have a fairly comprehensive cost model that is very user friendly. We can use that to vet some of the approaches, to see what makes sense.
Then there are chip and equipment standards – that requires quite a lot of work.
We are very excited about this, because CMOS scaling faces issues. A lot of the scaling of CMOS has been evolutionary in nature. 3D could bring in a whole new dimension.