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Going 3D: IBM breaks into the Z dimension with through silicon via manufacturing

Posted on: 12-Apr-2007

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IBM announced today (April 12th) that it is in early manufacturing of 3D ICs that use through-silicon vias (TSVs), beginning a three-phased rollout of TSV-connected products that will culminate in multi-core microprocessors connected vertically to cache memory devices.
IBM said it expects to be the first commercial semiconductor company to use through-silicon vias to vertically connect ICs, kicking off a move into the Z dimension by a wider swathe of the semiconductor industry.
By the second half of this year, IBM foundry customers using its SiGe process in Burlington, Vt. will begin sampling TSV-enhanced power amplifiers used in wireless LANs, advanced radar solutions, and other wireless products, said Lisa Su, vice president of semiconductor research and development at IBM.
The TSVs will bring the PA die in close vertical proximity to a ground plane layer. These wireless products would use hundreds of through-silicon vias, with via diameters in the 200-micron range, to connect the PA device with the ground plane. Instead of connecting with wire bonds that have relatively high parasitics, the TSVs will allow much shorter and faster connections to ensure that the SiGe device is effectively grounded.
The approach etches vias rough three-thousandths of an inch deep in the SiGe PA chip to create connections to a backside metal layer . Tungsten will be used in the first phases, though electroplated copper may be used for MPUs that include copper metallization steps.
While many power amplifiers used in cellphones and other wireless applications are made in gallium-arsenide, SiGe-based products use less-expensive silicon wafers as the starting point. Also, more support logic can be integrated on to SiGe-based solutions.
“Our TSV technology will be used first in the wireless space. SiGe now is so high-speed that it has been necessary to add additional ground planes. We have gone through a number of iterations with our SiGe technology, and it clear what’s needed there. This vertical connection to the ground plane is an extra thing we can add which will give us significant differentiation. From a power efficiency standpoint, by adding a ground plane under the chip, the power efficiency increases by 40 percent. That makes SiGe very competitive with GaAs, at a much lower price and a higher level of integration,” Su said.
The next phase uses a similar approach, but with smaller vias at higher densities, to attack the power stabilization challenge for microprocessors. A 65-nm microprocessor would be connected, using C4 balls, to a 90-micron silicon interposer containing the TSVs.
The TSVs in the interposer layer would connect the MPU to a layer of capacitors, voltage regulators, and other passives, to improve power delivery to the Power MPU at the 45-nm node.
“As we go to multi-core microprocessors, the amount of coupling capacitance increases and power delivery becomes an issue. In some cases power delivery can vary by 5 percent across the chip. So the second application of this TSV technology is to improve the processor-conformant power delivery,” Su said.
 
Tomorrow: IBM takes through-silicon vias to the microprocessor-memory bandwidth challenge
 

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weQuest's are written by G Dan Hutcheson, his career spans more than thirty years, in which he became a well-known as a visionary for helping companies make businesses out of technology. This includes hundreds of successful programs involving product development, positioning, and launch in Semiconductor, Technology, Medicine, Energy, Business, High Tech, Enviorntment, Electronics, healthcare and Business devisions.

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