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Is the Mears "superlattice" a knob worth turning?

Posted on: 15-Jan-2007

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Companies large and small try to entice customers to pay for their new technologies, without giving away their proprietary knowledge to competitors.
In that sense, Mears LLC, is in good company. After all, any company that bases its livelihood solely on its intellectual property (IP) must be particularly careful about how it discloses its secret sauce.
Mears is making fairly large claims, i.e., that it is has developed a way to reduce gate leakage by 60 to 80 percent by introducing a “superlattice” to the channel. At the same time, it is being fairly secretive about exactly how it achieves such dramatic gains.
Bob Mears has credentials: he taught electronic engineering at Cambridge University, where he came up with ideas about how to re-engineer the silicon bandgap by epitaxially depositing silicon in the channel region. Since 2001 he has been working to turn his ideas into a licensable IP package.
The Mears Silicon Technology introduces an epitaxial step inserted into a standard CMOS flow, prior to the gate formation. The 15-person company, based in Waltham, Mass., has worked with the Advanced Technology Development Fab (ATDF), the contract fab subsidiary of Sematech in Austin, running more than a thousand test wafers. Mears contracted with epi specialist Lawrence Semiconductor Research Laboratory, Inc. during the development process. Mears also worked with ASM International, using its Epsilon deposition tool. That is significant in that no proprietary tooling is needed. ASM’s Epsilon is the same tool that Mears’ customers will use to create the superlattice.
Mears said the MST silicon is deposited by a proprietary recipe, creating a laminate about 100 Angstroms thick which is more two-dimensional than a conventional epitaxial silicon recipe. While this superlattice is still a single crystal, the atomic planes are slightly stepped off from each other in sheets, like graphite.
Mears claims this does two things: in the horizontal or lateral plane it reduces the effective mass and improves the mobility. In the vertical direction mobility is inhibited, because the effective mass is made higher, making it harder for electrons and holes to travel in the vertical direction through the proprietary epitaxial  layer. And that, Mears claims, has a direct bearing on gate leakage.
“The various tunneling mechanisms that result in gate leakage all have an impedance matching condition as carriers go across the junction. By making the effective mass higher in the superlattice, a mismatch occurs which is like an impedance match. This mismatch can reduce the leakage in the vertical direction and enhance the drive current through the channel,” he said.
What about defects?
“Everybody wants to know about defectivity,” Mears acknowledged. “We have put the wafers through the standard defect measurements, and we don’t see the same sort of defects that we see with strained silicon,” he said.
Are there parallels with strained silicon? That’s what makes this company so enticing. If Mears has come up with something half as important as strained silicon, the chip industry needs to carefully check out this company’s claims. Read United States Patent Application 0060273299 and let me know, please, if you think Mears is turning an important knob.

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About weQuest:
weQuest's are written by G Dan Hutcheson, his career spans more than thirty years, in which he became a well-known as a visionary for helping companies make businesses out of technology. This includes hundreds of successful programs involving product development, positioning, and launch in Semiconductor, Technology, Medicine, Energy, Business, High Tech, Enviorntment, Electronics, healthcare and Business devisions.

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